Abstract: A data recovery method to improve storage consistency of a distributed storage system includes: receiving a recovery message from a storage node after a fault recovery of the faulty storage node; obtaining N lost erasure coding (EC) blocks of the faulty storage node through computation according to EC blocks stored by non-faulty storage nodes; sequentially sending N lost EC blocks to the faulty storage node for storage. In the process of sequentially sending the N lost EC blocks to the faulty storage node, when it is determined that for a first EC block that is to be stored by the faulty storage node, a second EC block having a same key value as the first EC block exists in the lost EC blocks, after the faulty storage node stores the second EC block, the first EC block is sent to the faulty storage node to store.

Abstract: A device and method for incrementally updating the error detecting and correcting bits for an error corrected block of data in a cross point memory array is disclosed. When an error corrected block of data is modified, only the modified data bits and the incrementally updated error detecting and correcting bits are changed in the cross point memory device for improved performant and reduced impact to device endurance.

Abstract: A decoding device includes a reception unit and a correction unit. The reception unit receives data obtained by segmenting transmit data into multiples of a predetermined number of bits, calculating parity data for each bit position in a segment, attaching the parity data to the transmit data, and performing bit number conversion coding on the transmit data so that a ratio of a frequency of occurrence of a first code and a frequency of occurrence of a second code becomes a predetermined ratio. The correction unit corrects a 1-bit error in the received data on a basis of a decoding error occurring in the bit number conversion coding performed on the data received by the reception unit, and a parity error detected according to the parity data from the received data obtained by decoding the data.

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

Abstract: Technologies are generally described for systems, devices and methods effective to reduce power consumption in flash memory. In some examples, a bit error rate estimator module may estimate two or more bit error rates. The two or more bit error rates may be associated with application of respective voltages to read from a memory. A voltage setup module may be configured to be in communication with the bit error rate estimator module. The voltage setup module may be configured to select a voltage to read from the memory. The voltage may be selected based on the two or more bit error rates and based on an error correction level. The error correction level may be a tolerance level available to correct read errors from the memory.

Abstract: A physical layer (PHY) preamble is generated, the PHY preamble defined by a first wireless communication protocol and including a first portion that corresponds to a legacy PHY preamble defined by a second, legacy wireless communication protocol. The PHY preamble also includes a second portion that is defined by the first wireless communication protocol. Error detection information is generated using a first field in the first portion of the PHY preamble. The second portion of the PHY preamble is generated to include the error detection information in a second field. The PHY data unit is generated so that the PHY data unit includes the PHY preamble.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Embodiments of the invention provide a scan test system for an integrated circuit comprising multiple processing elements. The system comprises at least one scan input component and at least one scan clock component. Each scan input component is configured to provide a scan input to at least two processing elements. Each scan clock component is configured to provide a scan clock signal to at least two processing elements. The system further comprises at least one scan select component for selectively enabling a scan of at least one processing element. Each processing element is configured to scan in a scan input and scan out a scan output when said the processing element is scan-enabled. The system further comprises an exclusive-OR tree comprising multiple exclusive-OR logic gates. The said exclusive-OR tree generates a parity value representing a parity of all scan outputs scanned out from all scan-enabled processing elements.

Abstract: A method of processing data in a telecommunications system enabling dynamic adaptation of the quantity of data to transmit. The data is organized into a set of packets contained in a first layer of a communication model. The method includes a first step of passage of an item of information indicating the size of each packet or representative of this size between the first layer and a second layer. It also includes a second step of encapsulation of the packet and of passage of the packet between the first layer and the second layer in a container the size of which is adapted to the information indicating the size of a packet or representative of this size. The method finally includes a third step of application of a block error correcting code to the data contained in the container, the correcting code adapting dynamically to the size of the container.

Abstract: A method by which a signal transmission device transmits packets in a communication system is provided. The method includes the operations of, generating a source symbol block including one or more source symbols having the same length by using a source packet block including one or more source packets; generating a restoration symbol block generated using one or more restoration symbols by performing a forward error correction (FEC) coding operation on the source symbol block; generating an FEC source packet including the source packets and an FEC payload identifier (ID) and transmitting the FEC source packet to a lower protocol; generating an FEC restoration packet including one or more of the restoration symbols and the FEC payload ID and transmitting the FEC restoration packet to the lower protocol; and transmitting FEC configuration information including information on the source symbol block generation operation to a receiver.

Abstract: A method and an apparatus for automatic retransmission and error recovery for packet oriented point to multipoint communication, which integrates adaptive and dynamic responsiveness for parameters for automatic retransmission using wireless communication, are provided. A wireless communication link is divided into a downstream portion and an upstream portion. Parameters are selected for automatic retransmission independently for the downstream portion and the upstream portion of the wireless communication link. A BSC controls the selection of parameters for automatic retransmission for all CPE within a cell. As part of a TDD frame, in which the BSC and the CPE share communication bandwidth using a TDMA technique, the BSC includes its selection of parameters for automatic retransmission to be used by CPE within a control section of the TDD frame.

Abstract: A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a demodulator an input code word with “strong” or “weak” solutions, decoding the input code word in a LDPC decoder using a predetermined dependence of a mean number of iterations on the signal-to-noise ratio, recording a number of iterations performed during the decoding of the input code word, averaging derived values of the number of iterations for a specified time interval, estimating a signal-to-noise ratio based on averaged derived values of the number of iterations and based on the predetermined dependence of the mean number of iterations on the signal-to-noise ratio, and generating an output decoded code word.

Abstract: In a transmitting device, in interchanging to interchange a code bit of an LDPC code in which a code length is 16200 bits and an encoding rate is 8/15 with a symbol bit of a symbol corresponding to any of 8 signal points defined by 8PSK, when 3 bits of code bits stored in three units of storages having a storage capacity of 16200/3 bits and read bit by bit from the units of storages are allocated to one symbol, a bit b0, a bit b1, and a bit b2 are interchanged with a bit y1, a bit y0, and a bit y2, respectively. A position of the interchanged code bit obtained from data transmitted from the transmitting device is returned to an original position. The present technology is applicable to a case of transmitting data using an LDPC code, for example.

Abstract: An apparatus includes a receiver configured to receive signals based on an application of test signals to a device under test (DUT). The apparatus further includes a processor and a memory storing computer-executable instructions, that when executed by the processor, cause the processor to generate multiple display frames based on a frequency domain analysis of the received signals. Each display frame of the multiple display frames corresponds to a frequency band of the received signals.

Abstract: The present disclosure relates to an apparatus and method supportive of distributed turbo coding based on relay network utilizing a noisy network coding scheme. For this, included is a relay node operating as a component encoder to relay a signal from a source node to a next node in a distributed turbo coding scheme. The relay node quantizes the signal transmitted from the source node and then interleaves the quantized signal using a predetermined pattern to distinguish the signal transmitted from the source node from a signal to be output from an opposing node, so that the signal transmitted from the source node is relayed to the next node based on a noisy network coding scheme.

Abstract: Various embodiments for data error recovery in a tape storage system, by a processor device, are provided. In one embodiment, a method comprises modifying erasure control configuration settings upon rereading a buffered dataset having passed through at least one microcode-initiated iterative decode cycle. X microcode-initiated iterative decode cycles are initiated on the buffered dataset while the tape is stopped, where x comprises at least one of a plurality of the microcode-initiated iterative decode cycles. The x microcode-initiated decode cycles are initiated on the buffered dataset until a predetermined error correction threshold is reached.

Abstract: An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.

Abstract: Embodiments of methods and systems are presented for handling PHY frames with multiple Reed-Solomon encoded blocks in PLC networks. A PHY frame is receive from a PLC device, the PHY frame comprising two or more Reed-Solomon encoded blocks. A first Reed-Solomon encoded block comprises a media access control (MAC) header. The first Reed-Solomon encoded block is decoded. An error-detection check is performed on the first decoded Reed-Solomon encoded block.

Abstract: A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet transmit circuit that employs a data framing module. The data framing module includes an input interface to receive Ethernet block data bits, and logic to aggregate the Ethernet block data bits in accordance with a 512/513B code. A forward error correction encoder is coupled to the logic to encode at least a first portion of the data bits to generate first error check bits. A Reed-Solomon (RS) encoder is coupled to the logic to encode at least a second portion of the data bits in accordance with a Reed-Solomon error code to generate second error check bits.

Abstract: Embodiments described herein include a computing system that permits partial writes into a memory element—e.g., a register on a processor. For example, the data to be written into the memory element may be spread across multiple sources. The register may receive data from two different sources at different times and perform two separate partial write commands to store the data. Embodiments herein generate an ECC value for each of the partial writes. That is, when storing the data of the first partial write, the computing system generates a first ECC value for the data in the first partial write and stores this value in the memory element. Later, when performing the second partial write, the computing system generates a second ECC value for this data which is also stored in the memory element.