Abstract: An error correcting encoder includes an error correcting data generator for receiving payload data belonging to a first category, for receiving payload data belonging to a second category, for determining first error correcting data for the first category payload data, and for determining second error correcting data for the second category payload data. The error correcting encoder further includes an interleaver for interleaving at least the second error correcting data and the second category payload data with each other. A first interleaving length relative to an interleaving of the first error correcting data and the first category payload data differs from a second interleaving length relative to the interleaving of the second error correcting data and the second category payload data. A corresponding error correcting decoder and methods for error correcting encoding/decoding are also disclosed.

Abstract: A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.

Abstract: A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.

Abstract: The present invention discloses a multi-code Chien's search circuit for BCH codes with various values of m in GF(2m). The circuit includes: a combined matrix unit, a number of first multiplexers, a number of registers and a number of second multiplexers. By designing the Chien's search circuit having several Chien's search matrices, with peripheral components, it is able to achieve applications for different code rates, different code lengths and even different m in GF(2m).

Abstract: Certain aspects of the present disclosure provide methods and apparatus for enhancing error protection for wireless transmissions. The apparatus may generally include a processing system configured to generate a first error check value for a packet to be transmitted to another apparatus, the first error check value generated based on a remaining portion of the packet, and generate a second error check value for the packet based on information known or expected by the other apparatus and other information transmitted in the packet. The apparatus may also include a transmitter configured to transmit the packet to the other apparatus, the packet comprising the first and second error check values.

Abstract: There is provided an error correction method for a non-volatile memory. The method includes receiving a codeword read from the non-volatile memory, computing a reliability information for each bit of the codeword received, and performing a reduced-complexity soft-decision decoding (SDD) technique to decode the received codeword. In particular, the SDD technique includes forming a set of test patterns based on the reliability data, and determining whether to perform a HDD of a test pattern in the set of test patterns based on a distance between the test pattern and a candidate pattern. There is also provided an error correction module for a non-volatile memory and a memory system incorporating the error correction module.

Abstract: An integrated circuit device for correcting errors in data read from memory cells includes a decoder, an encoder and a data management module. The data management module is configured to select a correctable raw bit error rate limit from a plurality of raw bit error rate limits by changing a code-rate used by the encoder, wherein a virtual change to the decoder and the encoder occur to change the code rate.

Abstract: One embodiment provides a PHY having a Media Access Control (MAC) and a Forward Error Correction (FEC) decoder, capable of error detection and error correction for FEC encoded packets based on FEC parity data included in the FEC encoded packets. The FEC decoder is capable of being enabled into different configurations of different operations to perform on FEC parity data included in the FEC encoded packets. The different configurations having different respective associated latencies.

Abstract: An apparatus and method that prevent a bit error in a static random access memory (SRAM)-based Physically Unclonable function (PUF). The method for preventing an error in a PUF includes selecting any value, from a physically unclonable function based on a volatile memory device, as an input value, and checking a response corresponding to the selected input value, classifying cells having a plurality of bits corresponding to the response depending on frequency of error occurrence, calculating a number of white cells, in which an error does not occur, from classified results, and determining whether the number of white cells is greater than a preset threshold number of white cells, and selecting an input value of the physically unclonable function based on results of determination.

Abstract: A method of processing broadcast data in a broadcast transmitter. The method can include randomizing broadcast service data, first encoding the randomized broadcast service data to add parity data to the randomized broadcast service data, second encoding the first-encoded broadcast service data at a code rate of D/E (D<E and D and E are integers equal to or greater than 1, respectively), first interleaving the second-encoded broadcast service data, second interleaving the first-interleaved broadcast service data, encoding signaling data for signaling the broadcast service data, third interleaving the encoded signaling data, fourth interleaving the third-interleaved signaling data, and transmitting the second-interleaved broadcast service data and the fourth-interleaved signaling data through a frame. The frame includes known data, and the signaling data includes information for identifying the code rate and information related to the known data.

Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.

Abstract: Systems and methods for latches are presented. In one embodiment a system includes scan in propagation component, data propagation component, and control component. The scan in propagation component is operable to select between a scan in value and a recirculation value. The data propagation component is operable to select between a data value and results forwarded from the scan in propagation component, wherein results of the data propagation component are forwarded as the recirculation value to the scan in propagation component. The control component is operable to control an indication of a selection by the scan in propagation component and the data propagation component.

Abstract: A method of transmitting a broadcast signal includes encoding mobile service data to build a Reed-Solomon (RS) frame according to an RS frame mode, wherein the mobile service data is either a mobile service data of a base layer or a mobile service data of the base layer and at least one enhancement layer, wherein each layer is specified by a layer identifier, wherein a layer identifier value of the base layer is set to 0 and a layer identifier value of the at least one enhancement layer starts from 1; and encoding signaling data, wherein the signaling data includes fast information channel (FIC) data and transmission parameter channel (TPC) data, and the FIC data includes information for rapid mobile service acquisition.

Abstract: A memory device includes a memory cell unit, a bit line unit and a buffering unit. The memory cell unit includes a plurality of memory cell groups. Each memory cell group includes at least one memory cell for storing data therein. The bit line unit includes a plurality of first bit lines each coupled to the at least one memory cell of a respective memory cell group, and a second bit line for transmitting to-be-read data. The buffering unit includes a plurality of two-state buffers. Each two-state buffer has an input terminal coupled to a respective first bit line, and an output terminal coupled to the second bit line. The memory device does not require a sense amplifier, and thus consumes relatively small power. The memory device can operate at a relatively high frequency when properly configured.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: A technique for operating a data storage system that includes a non-volatile memory array controlled by a controller includes storing, in the non-volatile memory array, first data whose frequency of access is above a first access level in a bandwidth optimized code word. Second data whose frequency of access is below a second access level is stored in the non-volatile memory in a code rate optimized code word.

Abstract: Aspects of the present disclosure are directed to apparatuses and methods capable of selective acknowledgement of packets from an access probe. In one aspect, an apparatus includes: a transceiver configured to receive a set of frames associated with an access probe message from a wireless node, wherein the access probe message includes a plurality of frames, and the set of frames comprises a subset of the plurality of frames; and a processing system configured to generate a selective acknowledgement message based on a determination of whether each frame in the set of frames is received correctly. The acknowledgement includes an indication of receipt for at least one frame in the set of frames. The transceiver can transmit the selective acknowledgement message with an identifier assigned to the wireless node to allow tracking of a response. Other aspects, embodiments, and features are also claimed and described.

Abstract: Data stored in a nonvolatile memory is selectively sampled based on write-erase cycle counts of blocks. Blocks with the lowest write-erase cycle counts are sampled to determine an error rate which is compared with a limit. If the error rate exceeds the limit then the sample is expanded to include blocks with the next lowest write-erase cycle counts.

Abstract: A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing the first group of main blocks or the second group of main blocks, a repair logic suitable for enabling a replacement signal when one or more of the second group of main blocks are defective, a control logic suitable for generating an address for the second group of main blocks in response to a dedicated command for access to one or more of the second group of main blocks, and an address decoder suitable for selecting one or more of the redundancy blocks based on the address for the second group of main blocks when the replacement signal is enabled.

Abstract: A method for parallel multi-dimensional encoding, the method may include receiving or generating a first version of a group of bits and a second version of the group of bits, wherein the first and second versions differ from each other by an arrangement of bits of the data unit; selecting a first set of bits of the first version and a second set of bits of the second version; encoding, in parallel, the first set of bits and the second set of bits; wherein the encoding of the second set of bits is responsive to the second set of bits and a first redundancy result of the encoding of the first set of bits; and wherein the encoding of the first set of bits is responsive to the first set of bits and to a second redundancy result of the encoding of the second set of bits.