Abstract: Configuring spare sections in a system having a plurality of devices and having a plurality of erasure encoding groups, each of the devices having a plurality of sections and each of the groups having a plurality of members located on the sections of the devices, includes configuring the system to have a plurality of erasure encoding groups with no spare sections, ordering the groups according to desirability of converting members of each of the groups into spare sections, converting members of a subset of the groups into spare sections according to ordering of the groups, and determining if the spare sections for the system provide sufficient coverage for the system in response to failure of each of the devices. The erasure encoding may be a RAID encoding.

Abstract: A computer memory access method includes: receiving external data with a prefetching length; determining that the external data includes a masked data portion; at the time of a write enable signal being triggered, writing an unmasked data portion of the external data into a data storage unit of a computer memory by a writing unit; triggering a read enable signal at the time of the write enable signal being triggered and reading the unmasked data portion from the data storage unit by a reading unit while reading a third data portion corresponding to the masked data portion from the data storage unit; merging the unmasked data portion and the third data portion to a merged data and generating parity bits from the merged data by an error correction code encoding circuit; and writing the parity bits into a parity bit storage unit of the computer memory.

Abstract: A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.

Abstract: A communication control apparatus includes a first obtaining section, a second obtaining section, and a control section. The first obtaining section is configured to obtain a first communication status indicating a frequency of occurrence of data loss during first data communication from a first communication device to a second communication device. The second obtaining section is configured to obtain a second communication status indicating a frequency of occurrence of data loss during second data communication from the second communication device to the first communication device. The control section is configured to control transmission processing relating to transmission from the second communication device to the first communication device in accordance with the first communication status and the second communication status.

Abstract: A group of one or more solid state storage cells is programmed. A predetermined amount of time after the group of solid state storage cells is programmed, the group of solid state storage cells is read to obtain read data. Error correction decoding is performed on the read data and the group of solid state storage cells is assessed for wear related degradation based at least in part on the error correction decoding.

Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.

Abstract: Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.

Abstract: An integrated circuit memory device includes an array of non-volatile, charge trapping memory cells, configured to store data values in memory cells in the array using threshold states, including a higher threshold state. Retention check logic executes to identify memory cells in the higher threshold state which fail a threshold retention check. Also, logic is provided to reprogram the identified memory cells.

Abstract: Disclosed are a method for transmitting and receiving data in a wireless access system supporting relay nodes, and an apparatus for same. In particular, the present invention comprises the steps of: sending a request for a retransmission to an adjacent second terminal, in case the recovery of data from a first signal received from a base station fails due to interference by the second terminal adjacent to a first terminal; the first terminal receiving a second signal from the second terminal; and the first terminal recovering data from the first signal, using the second signal, wherein the base station schedules a terminal other than the first and second terminals at the point of transmitting the second signal.

Abstract: Embodiments of the present disclosure relate to a system and computer program product for managing a microcode error in a storage operation. Embodiments include receiving an error code that corresponds to the microcode error and receiving a received error path signature for the error code. Embodiments also include identifying a metadata error path signature for the error code within a metadata table and determining whether the received error path signature for the error code substantially matches the metadata error path signature for the error code. Embodiments also include initiating a mitigation action in response to the received error path signature for the error code substantially matching the metadata error path signature for the error code.

Abstract: Methods and devices are provided wherein feedback is included in a checksum. An example method includes communicating between a first device and a second device. The method further includes including feedback information used by the first device as input to a checksum calculation, wherein the feedback information is not communicated concurrently with the checksum from the first device to the second device.

Abstract: Methods and apparatus of enhanced status retransmission in wireless communication include receiving at least a first portion of a reconfiguration message from a network entity. The methods and apparatus further include detecting an absent second portion of the reconfiguration message. Moreover, the methods and apparatus include sending a retransmission request to the network entity based at least in part on the detecting of the absent second portion of the reconfiguration message and irrespective of a state of a status prohibit timer. Additionally, The methods and apparatus include triggering a status prohibit timer disregard state for at least a portion of a status prohibit time period of the status prohibit timer, wherein the status prohibit timer disregard state permits the sending of the retransmission request during the status prohibit timer period.

Abstract: Access terminals are adapted to facilitate closed-loop transmit diversity in wireless communications systems. According to one example, an access terminal can calculate an uplink error rate for even slot indexes and a separate uplink error rate for odd slot indexes in an uplink frame to be transmitted. A respective downlink error rate can be estimated for an in-phase (I) component and a quadrature-phase (Q) component of a downlink transmission. The access terminal may further estimate a phase-related weight that was applied to the downlink transmission based on the downlink error rates and the uplink error rates. Other aspects, embodiments, and features are also included.

Abstract: Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received.

Abstract: Provided is a method of decoding a low-density parity-check code (LDPC). The decoding method including an initialization process, a check node update process, a variable node update process, a tentative decoding process, and a parity check process, for a plurality of check nodes and a plurality of variable nodes, further includes detecting at least one inactive variable nodes that do not require variable node update among the variable nodes, the variable node update process is performed only on active variable nodes except for the inactive variable node, and the check node update process is performed without using the inactive variable node.

Abstract: A method for measuring a signal-to-noise ratio when decoding Low Density Parity Check (LDPC) codes is provided. The method includes receiving from an input of a demodulator an input code word with “strong” or “weak” solutions, decoding the input code word in a LDPC decoder using a predetermined dependence of a mean number of iterations on the signal-to-noise ratio, recording a number of iterations performed during the decoding of the input code word, averaging derived values of the number of iterations for a specified time interval, estimating a signal-to-noise ratio based on averaged derived values of the number of iterations and based on the predetermined dependence of the mean number of iterations on the signal-to-noise ratio, and generating an output decoded code word.

Abstract: A high speed USB memory controller includes a microprocessor, flash memory, memory buffers directly accessible to the microprocessor and flash memory, and a USB interface for writing data directly into the memory buffers. This allows devices with multiple flash die to operate at full bus speed.

Abstract: One embodiment of the present invention provides a system for facilitating network coding in an information centric network. During operation, the system sends, from a content consumer node, one or more interests for a plurality of chunks associated with a content object. A respective interest indicates the corresponding chunk using a hierarchically structured variable length identifier which comprises contiguous name components ordered from a most general level to a most specific level. In response, the system then receives a number of network-coded data packets, wherein a respective data packet corresponds to an independent linear combination of all the chunks for the content object. The system subsequently re-constructs the content object based on the received data packets.

Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Abstract: A method of reading data in a memory system including a non-volatile memory device, includes reading first data stored in a first block using a first read scheme capable of detecting/correcting an error in the first data, and upon determining an uncorrected error in the first data, setting the first block as a first temporary bad block and reading second data stored in the first temporary bad block using a second read scheme different from the first read scheme.