Patents Examined by Eugene Lee
  • Patent number: 10854789
    Abstract: A light-emitting device includes a first lead having a first lateral surface, a second lead having a second lateral surface, and a resin portion. The first lateral surface of a first lead facing a second lead has a first recess that is recessed so as to be away from the second lead toward the first lead in a top view, and is continuous with an end of a first groove. The second lateral surface of the second lead facing the first lead has a second recess that is recessed so as to be away from the first lead toward the second lead in the top view, and is continuous with an end of a second groove. In the top view, a part of the resin portion is continuously disposed between the end of the first groove and the end of the second groove.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 1, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Ryosuke Wakaki
  • Patent number: 10854649
    Abstract: An image sensor may include unit pixel blocks with each having pixels for sensing incident light. Each unit pixel block may include a first sub pixel block including a first floating diffusion, a second sub pixel block including a second floating diffusion, and a common transistor block including a first drive transistor adjacent to the first floating diffusion and a second drive transistor adjacent to the second floating diffusion. The first and second floating diffusions may be electrically coupled in common to the first and second drive transistors.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventor: Pyong-Su Kwag
  • Patent number: 10833091
    Abstract: A ferroelectric memory is provided. The ferroelectric memory includes a first electrode, a second electrode opposite to the first electrode, at least one ferroelectric layer disposed between the first electrode and the second electrode, and at least one antiferroelectric layer disposed between the first electrode and the second electrode, wherein the antiferroelectric layer is in contact with the ferroelectric layer.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: November 10, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-De Lin, Heng-Yuan Lee, Po-Chun Yeh, Chih-Yao Wang, Hsin-Yun Yang
  • Patent number: 10832920
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer on the semiconductor substrate and having an exposed portion of a lower surface, a capping layer on the first semiconductor layer, a second semiconductor layer below the capping layer and having a side surface substantially in full contact with the capping layer, a cavity defined by the first semiconductor layer, the second semiconductor layer, and the capping layer, and a through-hole passing through the capping layer and the second semiconductor layer and extending to the cavity.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: November 10, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Patent number: 10811311
    Abstract: An element isolation structure includes a substrate defining a trench including an upper trench and a lower trench in communication with each other, the substrate including an inclined sidewall that forms the upper and lower trench; a first thin film liner on the substrate and conforming to the substrate, the first thin film liner having a substantially uniform thickness trench; a second thin film liner pattern selectively on a lower portion of the first thin film liner within a volume defined by the lower trench, the second thin film liner pattern having a substantially uniform thickness; a lower isolation layer formed on the second thin film liner pattern and substantially filling the volume defined by the lower trench; and an upper isolation layer formed on an upper portion of the first thin film liner and the lower isolation layer and substantially filling a volume defined by the upper trench.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: October 20, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Dong Hoon Park, Jung Hyun Lee, Dae Il Kim, Bum Seok Kim, Jin Hyo Jung, Seung Ha Lee, Sang Yong Lee
  • Patent number: 10809627
    Abstract: An exposure mask includes an aligning portion and a boundary portion. The aligning portion may be aligned with pixel areas of a substrate and includes a first exposure member and a second exposure member. The boundary portion includes a first exposure element, a second exposure element, a third exposure element, and a fourth exposure element. The first exposure member, the first exposure element, and the second exposure element are positioned in a first row. The first exposure element is positioned between the first exposure member and the second exposure element and is larger than the second exposure element. The second exposure member, the third exposure element, and the fourth exposure element are positioned in a second row. The third exposure element is positioned between the second exposure member and the fourth exposure element and is smaller than the fourth exposure element. Each exposure member/element includes a light transmitter/blocker.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 20, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Inwoo Kim
  • Patent number: 10790417
    Abstract: In embodiments of the invention, a light emitting device includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A first wavelength converting layer is disposed in a path of light emitted by the light emitting layer. The first wavelength converting layer may be a wavelength converting ceramic. A second wavelength converting layer is fused to the first wavelength converting layer. The second wavelength converting layer may be a wavelength converting material disposed in glass.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Lumileds LLC
    Inventors: April Schricker, Oleg Borisovich Shchekin, Han Choi, Peter Josef Schmidt
  • Patent number: 10784337
    Abstract: A method of manufacturing a MOSFET is presented. The method includes forming the MOSFET wherein a source region and a drain region are unsymmetrical in structure, with the horizontal junction depth of the drain region greater than the source region, and the vertical junction depth of the drain region greater than the source region; the breakdown voltage of the device is raised by increasing the horizontal and vertical junction depths of the drain region, and the horizontal dimension of the device is diminished by reducing the horizontal and vertical junction depths of the source region. In one embodiment, the formed MOSFET includes a gate dielectric layer that is unsymmetrical in structure—and the GIDL effect in the device is reduced by increasing the thickness of the first gate dielectric section, and the driving current of the device is increased by reducing the thickness of the second gate dielectric section.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 22, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Yu Chen
  • Patent number: 10770310
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10763203
    Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventors: Amornthep Saiyajitara, Wiwat Tanwongwan, Nathapop Lappanitpullpol
  • Patent number: 10749088
    Abstract: A light emitting device includes a package having a recess including an opening, a bottom surface, and an inner lateral surface extending from the bottom surface. A covering member covers at least one of the bottom surface or the inner lateral surface. A light emitting element is mounted on the bottom surface and has a light emitting surface. A sealing member is provided in the recess to cover the light emitting surface and has a light output surface having a concave shape. The sealing member includes a light-transmissive material containing a fluorescent material. A first film is provided on a part of the light output surface of the sealing member to reflect a part of the light emitted from the light emitting element, another part of the light emitted from the light emitting element being configured to pass through the first film.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 18, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Takayuki Sano
  • Patent number: 10749064
    Abstract: The invention relates to a radiation detector comprising a stack of superimposed layers successively comprising: an absorbent layer configured to absorb the radiation and made from a first semiconductor material, a screen charges layer made from a semiconductor material having a second bandgap value, a transition layer made from a semiconductor material having a third bandgap value, and a transition layer made from a semiconductor material having a third bandgap value, the absorbent layer and the screen charges layer having a doping of a first type, the first window layer having a doping of a second type, a dopant density of the window layer being greater than the dopant density of the transition layer.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: August 18, 2020
    Assignees: THALES, COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Axel Evirgen, Jean-Luc Reverchon
  • Patent number: 10741414
    Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka, Yukinori Shima, Masahiko Hayakawa, Takashi Hamochi, Suzunosuke Hiraishi
  • Patent number: 10734315
    Abstract: A display device includes a substrate; a pixel connected to a gate line and a data line on the substrate; a connection unit connected to one of the gate line and the data line of the substrate; and a driving integrated circuit mounted on the connection unit. The connection unit includes: a lead line connected to the driving integrated circuit; and at least one first dummy line adjacent to a first side of the connection unit intersecting a side of the substrate, the first dummy line not connected to any line of the connection unit including the driving integrated circuit and the lead line.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: August 4, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Myongsoo Oh
  • Patent number: 10731273
    Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 4, 2020
    Assignee: Micron Technology, Inc.
    Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
  • Patent number: 10720563
    Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: July 21, 2020
    Assignee: Google LLC
    Inventors: Evan Jeffrey, Julian Shaw Kelly
  • Patent number: 10705123
    Abstract: A SiC semiconductor device is provided that is capable of improving the detection accuracy of the current value of a principal current detected by a current sensing portion by restraining heat from escaping from the current sensing portion to a wiring member joined to a sensing-side surface electrode. The semiconductor device 1 includes a SiC semiconductor substrate, a source portion 27 including a principal-current-side unit cell 34, a current sensing portion 26 including a sensing-side unit cell 40, a source-side surface electrode 5 disposed above the source portion 27, and a sensing-side surface electrode 6 that is disposed above the current sensing portion 26 and that has a sensing-side pad 15 to which a sensing-side wire is joined, and, in the semiconductor device 1, the sensing-side unit cell 40 is disposed so as to avoid being positioned directly under the sensing-side pad 15.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 7, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Katsuhisa Nagao
  • Patent number: 10707094
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: 10686061
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: June 16, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10672900
    Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: June 2, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Nakajima