Patents Examined by Eugene Lee
  • Patent number: 11189645
    Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 30, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
  • Patent number: 11188843
    Abstract: A quantum computing device includes multiple co-planar waveguide flux qubits, at least one coupler element arranged such that each co-planar waveguide flux qubit, of the multiple co-planar waveguide flux qubits, is operatively couplable to each other co-planar waveguide flux qubit, of the multiple co-planar waveguide flux qubits, of the quantum computing device, and a tuning quantum device, in which the tuning quantum device is in electrical contact with a first co-planar waveguide flux qubit of the plurality of co-planar waveguide flux qubits and with a second co-planar waveguide flux qubit of the plurality of co-planar waveguide flux qubits.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 30, 2021
    Assignee: Google LLC
    Inventors: Alireza Shabani Barzegar, Pedram Roushan, Yu Chen, Hartmut Neven
  • Patent number: 11171016
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: 11164852
    Abstract: A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11152595
    Abstract: A method for manufacturing a display device including providing a protection resin having a base resin, a first initiator, and a second initiator to the non-display area, irradiating light having a first wavelength region to the protection resin to form a preliminary protection layer, bending the flexible substrate so that the bending part has a first curvature radius, and additionally curing the preliminary protection layer to form a protection layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 19, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Myoung-ha Jeon, Jinho Kim, Hyeonjeong Oh, Kichang Lee
  • Patent number: 11133450
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 11133451
    Abstract: A device includes a first chip having a first circuit element, a first interconnect pad in electrical contact with the first circuit element, and a barrier layer on the first interconnect pad, a superconducting bump bond on the barrier layer, and a second chip joined to the first chip by the superconducting bump bond, the second chip having a first quantum circuit element, in which the superconducting bump bond provides an electrical connection between the first circuit element and the first quantum circuit element.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: September 28, 2021
    Assignee: Google LLC
    Inventors: Joshua Yousouf Mutus, Erik Anthony Lucero
  • Patent number: 11127733
    Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: September 21, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
  • Patent number: 11121224
    Abstract: An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ming-Yeh Chuang, Elizabeth Costner Stewart
  • Patent number: 11114469
    Abstract: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhou, Binbin Cao, Liangchen Yan, Dongfang Wang, Ce Zhao, Luke Ding, Jun Liu
  • Patent number: 11101335
    Abstract: An organic light-emitting display apparatus including a substrate; a pixel electrode on the substrate; a pixel-defining layer including an opening exposing at least a portion of the pixel electrode; an intermediate layer including a center area on the pixel electrode and a side area extending from the center area and arranged on the pixel-defining layer, the intermediate layer including one or more common layers and an emission layer; a protective layer covering top surfaces of the center area and the side area of the intermediate layer and exposing at least a portion of the pixel-defining layer; and an opposite electrode spaced apart from the intermediate layer by the protective layer and arranged on the protective layer and portions of the pixel-defining layer, the portions being exposed by the protective layer.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: August 24, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Duckjung Lee, Arong Kim, Jungsun Park, Hyunsung Bang, Jiyoung Choung
  • Patent number: 11101351
    Abstract: A method of manufacturing a group III nitride semiconductor substrate may comprise introducing group III element vacancies to a first region of the group III nitride semiconductor substrate. The method may comprise introducing an acceptor element to a second region of the group III nitride semiconductor substrate. The second region may contact the first region at least in part. The method may comprise performing annealing to activate the acceptor element in the second region.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 24, 2021
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Keita Kataoka, Tetsuo Narita
  • Patent number: 11088307
    Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: August 10, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Masahiko Kobayakawa
  • Patent number: 11088190
    Abstract: An optical semiconductor device includes a semiconductor substrate having a plurality of photoelectric conversion parts and having a trench formed to separate the plurality of photoelectric conversion parts from each other, an insulating layer formed on at least an inner surface of the trench, a boron layer formed on the insulating layer, and a metal layer formed on the boron layer.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 10, 2021
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Masaharu Muramatsu, Yasuhito Miyazaki, Hirotaka Takahashi
  • Patent number: 11075224
    Abstract: A display device includes a first substrate and a flexible circuit board. Data lines, scan lines, thin film transistors, gate contacts, and source contacts are disposed on the first substrate. The scan lines are intersected with the data lines. The thin film transistors are respectively connected to the data lines and the scan lines. The gate contacts are connected to the scan lines. The source contacts are connected to the data lines. The display device further includes first conductive patterns disposed on a side of the first substrate, and the first conductive patterns are connected to at least some of the gate contacts on the side of the first substrate. First pads of the flexible circuit board are connected to the first conductive patterns.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 27, 2021
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hao-An Chuang, Wen-Fang Sung
  • Patent number: 11062937
    Abstract: A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, and the bottom sacrificial layer is on a substrate. The bottom sacrificial layer is removed so as to create an opening under the stack, and a dummy gate anchors the stack. A support structure is formed in the opening, and the support structure includes an air gap and is positioned between the stack and the substrate. One or more layers are formed on the support structure. Source or drain regions are formed over the one or more layers, such that the source or drain regions are isolated from the substrate.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: July 13, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 11056558
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane opposite to the first plane; a gate electrode; a gate insulating layer provided between the first plane and the gate electrode; and a pair of first p-type impurity regions provided in the semiconductor layer on both sides of the gate electrode, containing boron, carbon, and germanium, having a bond structure of boron and carbon, having a first boron concentration and a first depth in a direction from the first plane toward the second plane, and having a distance between the first p-type impurity regions being a first distance.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Izumida, Takeshi Shimane, Tadayoshi Uechi
  • Patent number: 11049938
    Abstract: A PLDMOS transistor includes a substrate, a P-type drift region disposed on an upper surface of the substrate, a first body region of N-type conductivity, the first body region being disposed on one side of the drift region and having a channel region formed thereon, a drain extension region of P-type conductivity, the drain extension region being disposed on another side of the drift region and being spaced apart from the first body region, a P-type drain region disposed on the drain extension region, a gate structure disposed on the channel region, an N-type buried layer disposed under the drift region and first and second breakdown voltage increasing layers being configured to increase the breakdown voltage by providing reduced surface fields.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: June 29, 2021
    Assignee: DB HITEK CO., LTD.
    Inventor: Chang Eun Lee
  • Patent number: 11050002
    Abstract: A method for producing a semiconductor chip and a semiconductor chip are disclosed. In an embodiment, the method includes providing a semiconductor layer sequence having a first semiconductor layer and a second semiconductor layer, wherein the first semiconductor layer is formed as a p-conducting semiconductor region and the second semiconductor layer is formed as an n-conducting semiconductor region, or vice versa, forming at least one recess in the semiconductor layer sequence so that side surfaces of the first and second semiconductor layers are exposed, wherein the recess is multiple times wider than deep and applying an auxiliary layer for electrically contacting the second semiconductor layer, wherein the auxiliary layer at the side surfaces exposed.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: June 29, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Alexander F. Pfeuffer, Dominik Scholz
  • Patent number: 11031386
    Abstract: A semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type region selectively formed in the semiconductor layer, a second conductivity type peripheral impurity region formed around the second conductivity type region in the semiconductor layer, and a Schottky electrode that is formed on the semiconductor layer and that forms a Schottky junction portion between a first conductivity type part of the semiconductor layer and the Schottky electrode, and, in the semiconductor device, a pn junction portion between the peripheral impurity region and the first conductivity type part of the semiconductor layer has a higher withstand voltage than a Zener voltage VZ of a Zener diode made of a pn junction portion between the second conductivity type region and the first conductivity type part of the semiconductor layer.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: June 8, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Yoshiteru Nagai