Patents Examined by Eugene Lee
  • Patent number: 10366635
    Abstract: A flexible display device may include a substrate and a display unit provided over the substrate. The substrate may include: a first base layer, a second base layer provided over the first base layer, and a first barrier layer provided between the first and second base layers. A face of the first base layer is larger than a face of the second base layer and is parallel to the face of the second base layer.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 30, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyeonsik Kim, Chaungi Choi, Hyehyang Park, Eunyoung Lee, Joohee Jeon, Seungho Jung
  • Patent number: 10356293
    Abstract: Provided is an image sensor having a pixel region including a plurality of pixel blocks disposed in a matrix form, outer address markers around the pixel region, interspaces between the plurality of pixel blocks, and inner address markers disposed in the interspaces.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Jong Eun Kim, Namil Kim, Dae-Woo Kim, Changsu Park, Dong-Hyun Woo
  • Patent number: 10355168
    Abstract: A lighting device according to embodiments of the invention includes a substrate with a plurality of holes that extend from a surface of the substrate. A non-III-nitride material is disposed within the plurality of holes. The surface of the substrate is free of the non-III-nitride material. A semiconductor structure is grown on the surface of the substrate. The semiconductor structure includes a light emitting layer disposed between an n-type region and a p-type region.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: July 16, 2019
    Assignee: LUMILEDS LLC
    Inventor: Toni Lopez
  • Patent number: 10344398
    Abstract: Various embodiments include methods and apparatuses comprising methods for formation of and apparatuses including a source material for electronic devices. One such apparatus includes a vertical string of memory cells comprising a plurality of alternating levels of conductor and dielectric material, a semiconductor material extending through the plurality of alternating levels of conductor material and dielectric material, and a source material coupled to the semiconductor material. The source material includes a titanium nitride layer and a source polysilicon layer in direct contact with the titanium nitride layer. Other methods and apparatuses are disclosed.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: July 9, 2019
    Assignee: Micron Technology, Inc.
    Inventors: John Mark Meldrim, Yushi Hu, Yongjun Jeff Hu, Everett Allen McTeer
  • Patent number: 10340344
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate, a gate insulating film, and a gate electrode. The gate insulating film is provided as being in contact with the first main surface of the silicon carbide substrate. The gate electrode is provided on the gate insulating film such that the gate insulating film lies between the gate electrode and the silicon carbide substrate. In a first stress test in which a gate voltage of ?5 V is applied to the gate electrode for 100 hours at a temperature of 175° C., an absolute value of a difference between a first threshold voltage and a second threshold voltage is not more than 0.5 V, with a threshold voltage before the first stress test being defined as the first threshold voltage and a threshold voltage after the first stress test being defined as the second threshold voltage.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Sumitomo Electric Industries, Ltd., Renesas Electronics Corporation
    Inventors: Ryosuke Kubota, Shunsuke Yamada, Taku Horii, Takeyoshi Masuda, Daisuke Hamajima, So Tanaka, Shinji Kimura, Masayuki Kobayashi
  • Patent number: 10340205
    Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Ku-Feng Yang
  • Patent number: 10340426
    Abstract: A phosphor is provided, which has a composition of Sr1-xLiAl3N4:Ce3+x, wherein 0<x<0.1. Sr1-xLiAl3N4 is a host material, and Ce3+ is a luminescent center. The phosphor can be collocated with an excitation light source to be applied in an illumination device. On the other hand, the phosphor can be collocated with other phosphors of different colors to be applied in a white light illumination device.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 2, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Julius Jr. Liclican Leano, Ru-Shi Liu
  • Patent number: 10333108
    Abstract: It is an object of the invention to provide a light emitting device which can display a superior image in which luminescent color from each light emitting layer is beautifully displayed and power consumption is lowered in a light emitting element in which light emitting layers are stacked. One feature of the invention is that, in a light emitting element which comprises light emitting layers stacked between electrodes, each distance between each light emitting layer and an electrode is odd multiples of quarter wavelength with a range of plus or minus 10% thereof by controlling a thickness of a layer provided therebetween to enhance luminous output efficiency. Another feature of the invention is that a drive voltage is lowered using a high conductive material for the layer compared with a conventional element.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: June 25, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Takeshi Noda, Shunpei Yamazaki
  • Patent number: 10332949
    Abstract: Disclosed are a display apparatus and a method of manufacturing the same. The display apparatus includes a light emitting part including a plurality of light emitting diodes; and a thin film transistor (TFT) panel part configured to drive the plurality of light emitting diodes. A first side of the light emitting part and a first side of the TFT panel part are coupled to each other so as to face each other. The plurality of light emitting diodes are electrically connected to the plurality of TFTs, respectively.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: June 25, 2019
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Jong Ik Lee, Young Hyun Kim
  • Patent number: 10326008
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: June 18, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10319651
    Abstract: The present disclosure provides a shorting bar structure and a method for manufacturing the same, and a Thin Film Transistor (TFT) substrate. The shorting bar structure comprises: a test wire; a test probe contact part connected to the test wire and configured to be able to contact with a test probe; and at least one PN junction structure located between the test wire and at least one wire under test, and configured to allow a test signal to be unidirectionally transmittable in a direction from the test wire to the wire under test.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 11, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yong Wang, Jaeyoung Joo, Hongyan Guo, Yang Yu, Cheong Yo Seop, Zongtian Xie, Zengyang Jiang, Cundui Tang, Huailiang Wu
  • Patent number: 10312340
    Abstract: A semiconductor device includes a first transistor comprising a first dielectric film on a substrate and a first work function metal film of a first conductivity type on the first dielectric film, a second transistor comprising a second dielectric film on the substrate and a second work function metal film of the first conductivity type on the second dielectric film, and a third transistor comprising a third dielectric film on the substrate and a third work function metal film of the first conductivity type on the third dielectric film. The first dielectric film comprises a work function tuning material and the second dielectric film does not comprise the work function tuning material. The first work function metal film has different thickness than the third work function metal film. Related methods are also described.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wan-Don Kim, Oh-Seong Kwon, Hoon-Joo Na, Hyeok-Jun Son, Jae-Yeol Song, Sung-Kee Han, Sang-Jin Hyun
  • Patent number: 10312268
    Abstract: A display device is provided, which includes a substrate including a pixel region; a metal oxide semiconductor transistor disposed over the substrate and including: a metal oxide semiconductor layer, a first gate electrode overlapping with the metal oxide semiconductor layer; and a gate insulating layer disposed between the metal oxide semiconductor layer and the first gate electrode, and the gate insulating layer having a first opening, wherein the first opening and the pixel region overlap; a second insulating layer disposed over the metal oxide semiconductor layer and having a via and a second opening, wherein the second opening and the pixel region overlap; and a pixel electrode electrically connected to the metal oxide semiconductor layer through the via.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: June 4, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Tzu-Min Yan, Ming-Chang Lin, Kuan-Feng Lee
  • Patent number: 10312423
    Abstract: A light-emitting device includes a light-emitting element, a wavelength converting layer and a light-adjusting layer. The light-emitting element has a first upper surface, a bottom surface, and a lateral surface between the first upper surface and the bottom surface. The wavelength converting layer includes a plurality of wavelength converting particles, and has a second upper surface on the first upper surface. The light-adjusting layer surrounds the lateral surface and has a first composition or a second composition. The first composition includes a first binder and a plurality of first light-diffusing particles. The second composition includes a second binder, a plurality of second light-diffusing particles, and a plurality of light-scattering particles.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: June 4, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Ching-Tai Cheng, Lung-Kuan Lai, Ju-Lien Kuo, Chun-Hua Shih, Hsuan-Tzu Peng, Yih-Hua Renn
  • Patent number: 10312425
    Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: June 4, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Masahiko Kobayakawa
  • Patent number: 10304749
    Abstract: In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed through one or more layers deposited over the etch stop layer, the channel extending to the etch stop layer.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Christopher W. Petz, Philip M. Campbell, Wei Yeeng Ng, Kunal Bhaskar Shrotri, Saurabh Keshav, John Mark Meldrim, Prakash Rau Mokhna Rau, Tom Jibu John
  • Patent number: 10297669
    Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua Feng Chen, Shu-Hui Wang, Mu-Chi Chiang
  • Patent number: 10283700
    Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure also includes a top electrode formed over the MTJ cell; and a first sidewall spacer layer formed on a top surface of the MTJ cell and an outer sidewall surface of the top electrode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Lin, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10276634
    Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Lin, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10276402
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai