Abstract: A semiconductor device includes a bit line on a substrate, a gate electrode on the bit line, a gate insulation pattern on a sidewall of the gate electrode, a channel that contacts an upper surface of the bit line and a sidewall of the gate insulation pattern, an oxide semiconductor pattern that contacts an upper sidewall of the channel, and a contact plug that contacts an upper surface of the channel and an upper surface of the oxide semiconductor pattern. The channel includes an amorphous oxide semiconductor material. The oxide semiconductor pattern includes a crystalline oxide semiconductor material.

Abstract: A semiconductor chip or die is arranged on a first surface of a thermally conductive die pad of a substrate such as a leadframe. An encapsulation of insulating material in molded onto the die pad having the semiconductor die arranged on the first surface. At the second surface of the die pad, opposite the first surface, the encapsulation borders on the die pad at a borderline around the die pad. A recessed portion of the encapsulation is provided, for example, via laser ablation, at the borderline around the die pad. Thermally conductive material such as metal material is filled in the recessed portion of the encapsulation around the die pad. The surface area of the thermally conductive die pad is augmented by the filling of thermally conductive material in the recessed portion of the encapsulation thus improving thermal performance of the device.

Abstract: An element package includes a semiconductor element, a redistribution layer, a sealing resin body, and an insulating portion. The semiconductor element includes a semiconductor substrate having an element region and a scribe region, a main electrode and a pad disposed on a surface of the semiconductor substrate, and a protective film disposed above the element region on the surface of the semiconductor substrate. The sealing resin body seals the semiconductor element while exposing the main electrode and the pad. The insulating portion is disposed above the scribe region on the surface of the semiconductor element with a height not to exceed an outer peripheral edge portion of an upper surface of the protective film on the element region. The redistribution layer extends over the protective film and the insulating portion above the scribe region.

Abstract: An electronic device includes conductive leads, a conductive crossbar, and first and second bond wires. The conductive leads are arranged in a row along a side of a package structure and include a conductive first lead, a conductive second lead, and a conductive third lead. The first and second leads are non-adjacent, the third lead is between the first and second leads in the row, and the crossbar electrically connects the first and second leads. The first bond wire electrically connects a first conductive feature of a semiconductor die to one of the crossbar, the first lead, and the second lead, and the second bond wire electrically connects a second conductive feature of the semiconductor die to the third lead.

Abstract: Methods of depositing titanium silicide (TiSi) in the formation of semiconductor structures are described. The methods include thermal chemical vapor deposition (CVD) in which a semiconductor substrate in a semiconductor processing chamber is exposed to a titanium-containing precursor, a silicon-containing precursor, and hydrogen (H2) to deposit the titanium silicide (TiSi) layer directly on the semiconductor substrate. Methods of selectively depositing titanium silicide (TiSi) in the formation of semiconductor structures, e.g., an n-type transistor and a p-type transistor, are also described.

Abstract: According to the embodiment, in an insulating circuit board in which a conductor part is bonded to at least one surface of an insulating substrate, in XPS analysis of the carbon amount at the surface of the conductor part, the average value of the carbon amounts at any three locations is within the range of not less than 0 at % and not more than 70 at %. In XPS analysis of the oxygen amount of the conductor part surface, it is favorable for the average value of any three locations to be within the range of not less than 3 at % and not more than 50 at %.

Abstract: A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

Abstract: A display panel includes a backlight module including a substrate, a first light source member disposed on a surface of the substrate, a second light source member disposed on the surface of the substrate, and a third light source member disposed on the surface of the substrate, a color converter module disposed on the surface of the substrate and including a color converter layer, the color converter layer including a first pixel area corresponding to the first light source member, a second pixel area corresponding to the second light source member, a third pixel area corresponding to the third light source member, and a quantum dot disposed in at least one of the first pixel area, the second pixel area, and the third pixel area, and a first adhesive layer disposed between the color converter module and the backlight module.

Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region. The current blocking region is composed of a high-resistance layer. The source electrode forms a contact with the current blocking region.

Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.

Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.

Abstract: Examples of the present disclosure provide a package structure, the package structure including: a package substrate; a semiconductor device on the package substrate; and a molding layer over the semiconductor device, the molding layer having a plurality of grooves disposed at its surface.

Abstract: In some implementations of the invention, a silicon dioxide (SiO2) insulating layer added between islands of a top YBCO layer of a Josephson Junction isolates a contact layer from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, a SiO2 insulating layer added between islands of a bottom YBCO layer of adjacent Josephson Junctions isolates the contact layer or other components from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, an etch stop layer may be deposited over the islands of the top YBCO layer prior to adding the SiO2 insulating layer. This etch stop layer protects the top YBCO layer during the adding of the SiO2 insulating layer and during subsequent formation of a via through the SiO2 to the etch stop layer.

Abstract: A thin film transistor includes: a substrate; a gate electrode; an active layer including a first active pattern and a second active pattern, where the first active pattern includes a first active sub-pattern, the first active sub-pattern comprises a first active region and a first source-drain contact region, the first source-drain contact region is connected to the second active pattern through the first active region, the first active pattern includes a material of at least one of a metal oxide semiconductor, low-temperature polycrystalline silicon, and amorphous silicon, and the second active pattern includes a material of a semiconductor carbon nanotube; a source electrode and a drain electrode spaced apart from each other and connected to the active layer; and a passivation layer on a side of the second active pattern distal to the substrate. A method for manufacturing the thin film transistor and a circuit are further provided.

Abstract: A display device comprises a base substrate which is a base substrate having a display area and a non-display area positioned around the display area defined therein, and includes a substrate connection electrode penetrating the base substrate in the thickness direction, an etching stopper which is disposed on a first surface of the base substrate and that covers the substrate connection electrode, and a first pad disposed on a second surface opposite to the first surface of the base substrate and disposed overlapping a substrate through hole, wherein the substrate connection electrode is disposed in the display area, the substrate connection electrode is electrically connected to the etching stopper and the first pad, the etching stopper is electrically connected to the first pad through the substrate connection electrode, and the etching stopper includes a conductive material.

Abstract: Provided is a technology that enables reliable transfer of signal electric charges. This photodetection device includes a semiconductor layer having a first surface and a second surface located on opposite sides of the semiconductor layer in a thickness direction, a photoelectric conversion part provided in the semiconductor layer, first and second electric charge retaining parts provided adjacent to the first surface of the semiconductor layer, a first transfer transistor that transfers signal electric charges generated by photoelectric conversion in the photoelectric conversion part to the first electric charge retaining part, and a second transfer transistor that transfers the signal electric charges transferred by the first transfer transistor and retained in the first electric charge retaining part to the second electric charge retaining part.

Abstract: A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.

Abstract: A semiconductor encapsulation method, comprising: forming a protection layer on a front side of a chip to be encapsulated; arranging said chip, with the protection layer being formed on the front side thereof, on a carrier plate, wherein the front side of said chip faces upwards and a back side thereof faces the carrier plate; and encapsulating, on the carrier plate, said chip and the protection layer to form a plastic encapsulation layer. Further provided is a semiconductor encapsulation structure.

Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).