Patents Examined by Eugene Lee
  • Patent number: 11552213
    Abstract: A template for growing Group III-nitride semiconductor layers, a Group III-nitride semiconductor light emitting device and methods of manufacturing the same are provided. The template for growing Group III-nitride semiconductor layers includes a growth substrate having a first plane, a second plane opposite to the first plane and a groove extending inwards the growth substrate from the first plane, an insert for heat dissipation placed and secured in the groove, and a nucleation layer formed on a partially removed portion of the first plane.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 10, 2023
    Assignee: WAVELORD CO., LTD.
    Inventor: Sang Jeong An
  • Patent number: 11551988
    Abstract: An electronic component, or a precursor thereof, that comprises a curable organopolysiloxane composition or a cured product thereof is disclosed. The curable organopolysiloxane composition is generally curable through a hydrosilylation reaction and can be applied to at least one area by a microdroplet application device. The curable organopolysiloxane composition has a viscosity of no more than 2.0 Pa┬Ěs at a strain rate of 1,000 (1/s), and a viscosity at a strain rate of 0.1 (1/s) being a value no less than 50.0 times the viscosity at a strain rate of 1,000 (1/s). In particular, the area of application generally is a substantially circular area that fits within a frame no more than 1000 ?m in diameter, a linear area no more than 1000 ?m in line width, or a pattern configured from a combination of these areas.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: January 10, 2023
    Assignee: DOW TORAY CO., LTD.
    Inventor: Manabu Sutoh
  • Patent number: 11538730
    Abstract: A chip scale package structure of heat-dissipating type is provided and includes a board, a die fixed on and electrically coupled to the board, a thermally conductive adhesive sheet adhered to the die, and a package body formed on the board. The die has a heat-output surface arranged away from the board. The thermally conductive adhesive sheet is connected to at least 50% of an area of the heat-output surface. The package body covers and is connected to the die and entire of the surrounding lateral surface of the thermally conductive adhesive sheet. The die is embedded in the board, the thermally conductive adhesive sheet, and the package body. The heat-dissipating surface of the thermally conductive adhesive sheet is exposed from the package body, and a thermal conductivity of the thermally conductive adhesive sheet is at least 150% of a thermal conductivity of the package body.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: December 27, 2022
    Assignee: AZUREWAVE TECHNOLOGIES, INC.
    Inventors: Hsin-Yeh Huang, Chih-Hao Liao, Shu-Han Wu
  • Patent number: 11538976
    Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: December 27, 2022
    Assignee: Google LLC
    Inventors: Evan Jeffrey, Julian Shaw Kelly
  • Patent number: 11532710
    Abstract: A system and method for a Laterally Diffused Metal Oxide Semiconductor (LDMOS) with Shallow Trench Isolation (STI) in the backgate region of FET with trench contacts is provided. The backgate diffusion region of the FET is split in the middle of the source-backgate side of the LDMOS with a strip of STI. A contact can be drawn across STI strip. The contact etch can be etched through the STI fill. The contact barrier material and trench fill processes can create a metal-semiconductor contact in the outline of the STI.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: December 20, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Patent number: 11527633
    Abstract: A method for manufacturing a trench gate device includes: forming a trench in a substrate with a super junction structure; forming a gate dielectric layer in the trench; forming a polysilicon gate by filling a portion of the trench with polysilicon; forming an intermediate dielectric layer in the trench; forming an auxiliary polysilicon layer by filling a gap in the trench with polysilicon; forming a source region of the trench gate device in the substrate; depositing an interlayer dielectric layer, and forming contacts in the interlayer dielectric layer, wherein the polysilicon gate, the auxiliary polysilicon layer, and the source region are led out from the contacts; and connecting the led-out auxiliary polysilicon layer to the led-out source region.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: December 13, 2022
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventor: Longjie Zhao
  • Patent number: 11508873
    Abstract: There is provided a light emitting device including: a substrate; a laminated structure provided on the substrate and having a plurality of columnar portions, in which the columnar portion includes an n-type first semiconductor layer, a p-type second semiconductor layer, a light emitting layer provided between the first semiconductor layer and the second semiconductor layer, and a third semiconductor layer having a band gap larger than that of the light emitting layer, and the third semiconductor layer includes a first part provided between the light emitting layer and the second semiconductor layer, and a second part that is in contact with a side surface of the light emitting layer.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 22, 2022
    Inventors: Hiroki Nishioka, Katsumi Kishino
  • Patent number: 11502204
    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: November 15, 2022
    Assignee: Kioxia Corporation
    Inventors: Akifumi Gawase, Atsuko Sakata
  • Patent number: 11488895
    Abstract: In a semiconductor device, a first lead frame and a second lead frame are fixed to a metal conductor base by an organic insulating film made of a polyimide-based material. The organic insulating film satisfies relationships of tpress1>tcast1 and tpress2>tcast1, where tpress1 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the first lead frame, tpress2 is a thickness of a portion of the organic insulating film sandwiched between the metal conductor base and the second lead frame, and tcast1 is a thickness of a portion of the organic insulating film that is not sandwiched between the metal conductor base and the first lead frame and is not sandwiched between the metal conductor base and the second lead frame.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: November 1, 2022
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ishino, Hirokazu Sampei
  • Patent number: 11482531
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: October 25, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Jiahui Yuan, Senaka Kanakamedala, Raghuveer S. Makala, Dana Lee
  • Patent number: 11469163
    Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: October 11, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11462515
    Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 4, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11462476
    Abstract: An electronic device is disclosed. In an embodiment an electronic device includes at least one first carrier and at least one semiconductor chip, wherein the first carrier has a cavity in which the semiconductor chip is arranged.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: October 4, 2022
    Assignee: TDK ELECTRONICS AG
    Inventors: Thomas Feichtinger, Johann Pichler, Nele Reimer, Markus Koini, Manfred Schweinzger
  • Patent number: 11456247
    Abstract: A reliable semiconductor device is provided. The semiconductor device includes at least one die. The at least one die includes an integrated circuit region, a first recess region surrounding the integrated circuit region, and a second recess region surrounding the first recess region. A first recess is disposed in the first recess region and a second recess is disposed in the second recess region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: September 27, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Li-Han Lu
  • Patent number: 11437466
    Abstract: An avalanche-protected field effect transistor includes, within a semiconductor substrate, a body semiconductor layer and a doped body contact region having a doping of a first conductivity type, and a source region a drain region having a doping of a second conductivity type. A buried first-conductivity-type well may be located within the semiconductor substrate. The buried first-conductivity-type well underlies, and has an areal overlap in a plan view with, the drain region, and is vertically spaced apart from the drain region, and has a higher atomic concentration of dopants of the first conductivity type than the body semiconductor layer. The configuration of the field effect transistor induces more than 90% of impact ionization electrical charges during avalanche breakdown to flow from the source region, to pass through the buried first-conductivity-type well, and to impinge on a bottom surface of the drain region.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Liang-Yu Su, Hung-Chih Tsai, Ruey-Hsin Liu, Ming-Ta Lei, Chang-Tai Yang, Te-Yin Hsia, Yu-Chang Jong, Nan-Ying Yang
  • Patent number: 11437453
    Abstract: Disclosed are a display apparatus and a method of manufacturing the same. The display apparatus includes a light emitting part including a plurality of light emitting diodes; and a thin film transistor (TFT) panel part configured to drive the plurality of light emitting diodes. The plurality of light emitting diodes are electrically connected to the plurality of TFTs, respectively, by a layer disposed between the light emitting diode part and the TFT panel part.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: September 6, 2022
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Jong Ik Lee, Young Hyun Kim
  • Patent number: 11430924
    Abstract: A wavelength conversion component includes a plurality of wavelength conversion members, a plurality of transmission type optical members respectively disposed on the wavelength conversion members, and a first member including a plurality of wall portions respectively located between adjacent ones of the wavelength conversion members. A light emitting device includes such wavelength conversion component.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: August 30, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 11424356
    Abstract: A transistor having: a semiconductor; a first electrode in contact with the semiconductor; a second electrode in contact with the semiconductor; and a control electrode, disposed between the first electrode and the second electrode, for controlling a flow of carriers in a channel in the semiconductor between the first electrode and the second electrode. A first electric field is produced in the channel in response to an electrical voltage applied between the first electrode and the second electrode. A field plate, comprising a resistive material, is disposed over the channel. A voltage source is connected across portions of the resistive field plate material for producing second electric field across such portions of the resistor, such second electric field being coupled into the channel to modify one or more peaks of the first electric field in the channel.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 23, 2022
    Assignee: Raytheon Company
    Inventors: Brian Thomas Appleton, Jr., Casey Alan Howsare
  • Patent number: 11404615
    Abstract: A light emitting device includes a light emitting element, a wavelength conversion member, a reflecting member and a covering member. The light emitting element has a top surface and lateral surfaces. The wavelength conversion member has a top surface, a bottom surface, and lateral surfaces, with the bottom surface of the wavelength conversion member facing the top surface of the light emitting element. The reflecting member surrounds the lateral surfaces of the light emitting element and the lateral surfaces of the wavelength conversion member. The reflecting member has a top surface. The covering member covers the top surface of the wavelength conversion member and the top surface of the reflecting member. The covering member contains a pigment or a dye so that a body color of the covering member is the same or a similar color as a body color of the wavelength conversion member.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: August 2, 2022
    Assignee: NICHIA CORPORATION
    Inventor: Hirosuke Hayashi
  • Patent number: 11398557
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first well, a second well, an isolation structure, a first field plate, a gate structure, a drain structure, and a source structure. The first well and the second well adjoin each other. The first well and the second well are disposed in the substrate. The isolation structure is disposed on the first well. The first field plate is disposed on the isolation structure. The gate structure crosses the first well and the second well, and an opening is defined between the first field plate and the gate structure to expose an edge of the isolation structure adjacent to the gate structure. The drain structure is disposed in the first well. The source structure is disposed in the second well.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 26, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yi-Ching Chung, Jui-Chun Chang, Fu-Chun Tseng, Yu-Ping Ho