Patents Examined by Eugene Lee
  • Patent number: 11996344
    Abstract: A semiconductor device includes: a semiconductor element having a first main electrode and a second main electrode; a first heat dissipation member and a second heat dissipation member; and a lead frame including a first main terminal connected to the first heat dissipation member and a second main terminal connected to the second main electrode. The second main terminal includes a connection portion connected with the second main electrode, a facing portion extending from the connection portion and facing the first heat dissipation member, and a non-facing portion. The non-facing portion and the first main terminal are arranged in a direction orthogonal to a thickness direction. A side surface of the first main terminal and a side surface of the non-facing portion of the second main terminal face each other.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: May 28, 2024
    Assignee: DENSO CORPORATION
    Inventors: Shoichiro Omae, Hiroshi Ishino
  • Patent number: 11990574
    Abstract: In an embodiment, a method for producing optoelectronic semiconductor devices includes applying a temporal spacer to protect a light-exit face of an optoelectronic semiconductor chip by applying a photoresist onto a first carrier, subsequently developing the photoresist in places thereby forming the temporal spacer and subsequently mounting the optoelectronic semiconductor chip onto a side of the temporal spacer facing away from the first carrier, forming a reflector in a lateral direction directly around the optoelectronic semiconductor chip and around the temporal spacer, subsequently removing the temporal spacer so that the reflector extends beyond the light-exit face and applying an optical element onto the reflector so that a gap exists between the light-exit face and a light-entrance face of the optical element.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: May 21, 2024
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Choo Kean Lim, Xiao Fen Hoo, Wan Leng Lim, Ai Cheng Chan
  • Patent number: 11991934
    Abstract: A quantum processor includes: a first chip comprising a qubit array, in which a plurality of qubits within the qubit array define an enclosed region on the first chip, in which each qubit of the plurality of qubits that define the enclosed region is arranged to directly electromagnetically couple to an adjacent qubit of the plurality of qubits that define the enclosed region, and in which each qubit of the qubit array comprises at least two superconductor islands, and a second chip bonded to the first chip, the second chip including one or more qubit control elements, in which the qubit control elements are positioned directly over the enclosed region of the first chip.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: May 21, 2024
    Assignee: Google LLC
    Inventors: Evan Jeffrey, Julian Shaw Kelly
  • Patent number: 11990505
    Abstract: A transient-voltage-suppression protection device and a manufacturing process therefor, and an electronic product. The transient-voltage-suppression protection device includes a substrate, a first trap, a second trap, a first injection region, and a second injection region, where the first trap and the second trap are sequentially arranged on the substrate from left to right at an interval, have a same doping type that is opposite to a doping type of the substrate, and are respectively provided with the first injection region and the second injection region with opposite doping types. The electronic product includes the transient-voltage-suppression protection device. In the solutions described, protection can be triggered and started at a lower voltage; the capacitance is small, and the manufacturing process is simple.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: May 21, 2024
    Assignee: WILL SEMICONDUCTOR CO., LTD.SHANGHAI
    Inventors: Fusheng Zhang, Chengzong Xu
  • Patent number: 11990470
    Abstract: An apparatus includes a first plate, a second plate, a third plate, a ferroelectric dielectric, and a paraelectric dielectric. The ferroelectric dielectric is between the first plate and the second plate such that the first plate, the ferroelectric dielectric, and the second plate form a first capacitor. The paraelectric dielectric is between the second plate and the third plate such that the second plate, the paraelectric dielectric, and the third plate form a second capacitor.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 21, 2024
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Reinaldo Vega, Cheng Chi, Praneet Adusumilli
  • Patent number: 11985856
    Abstract: A display apparatus and a method of manufacturing the same. The display apparatus includes a light emitting part including a plurality of light emitting diodes; and a thin film transistor (TFT) panel part configured to drive the plurality of light emitting diodes. The plurality of light emitting diodes are electrically connected to the plurality of TFTs, respectively, by a layer disposed between the light emitting diode part and the TFT panel part.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: May 14, 2024
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Motonobu Takeya, Jong Ik Lee, Young Hyun Kim
  • Patent number: 11978807
    Abstract: Provided is a semiconductor device of the embodiment including: an oxide semiconductor layer; a gate electrode; a first electrode electrically connected to one portion of the oxide semiconductor layer, the first electrode including a first region, second region, a third region, and a fourth region, the first region disposed between the first portion and the second region, the first region disposed between the third region and the fourth region, the first region containing at least one element of In, Zn, Sn or Cd, and oxygen, the second region containing at least one metal element of Ti, Ta, W, or Ru, the third region and the fourth region containing the at least one metal element and oxygen, the third region and the fourth region having an atomic concentration of oxygen higher than that of the second region; and a second electrode electrically connected to another portion of the oxide semiconductor layer.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: May 7, 2024
    Assignee: Kioxia Corporation
    Inventors: Akifumi Gawase, Atsuko Sakata
  • Patent number: 11955537
    Abstract: A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.
    Type: Grant
    Filed: August 26, 2022
    Date of Patent: April 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 11955412
    Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: April 9, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11948870
    Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: April 2, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11948849
    Abstract: A package-embedded board includes: a core layer having a through-hole portion; a package at least partially disposed in the through-hole portion and including a die pad, an electronic component disposed on the die pad, and a molded portion covering the electronic component; and a core insulating material disposed in the through-hole portion and covering the core layer and the package.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Koo Woong Jeong
  • Patent number: 11935799
    Abstract: Disclosed herein are integrated circuit (IC) package lids with polymer features, as well as related methods and devices. For example, in some embodiments, an IC package may include a package substrate, a lid, and a die between the package substrate and the lid. A foot or rib of the lid may include a polymer material.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Elah Bozorg-Grayeli, Taylor William Gaines, Frederick W. Atadana, Sergio Antonio Chan Arguedas, Robert F. Cheney
  • Patent number: 11929207
    Abstract: A capacitor includes: a plurality of bottom electrodes; a dielectric layer formed over the bottom electrodes; and a top electrode formed over the dielectric layer, wherein the top electrode includes a carbon-containing material and a germanium-containing material that fill a gap between the bottom electrodes.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventor: Seung-Muk Kim
  • Patent number: 11923269
    Abstract: An optical module includes an optoelectronic assembly and a heat spreader. The optoelectronic assembly includes a flat, rigid substrate, an array of electrical contacts positioned on a first portion of the substrate, and an optoelectronics assemblage that is electrically connected to the array of contacts and is positioned apart from the array of electrical contacts. The heat spreader is comprised of a thermally conductive material and comprises a second portion that is structurally connected to the first portion and a third portion that is thermally connected to the optoelectronics assemblage.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: March 5, 2024
    Assignee: International Business Machines Corporation
    Inventors: Mark D. Schultz, Fuad Elias Doany, Benjamin Giles Lee, Daniel M. Kuchta, Christian Wilhelmus Baks
  • Patent number: 11916176
    Abstract: A wavelength conversion component includes a plurality of semiconductor multilayer film segments, a first member arranged between adjacent ones of the semiconductor multilayer film segments, and a substrate disposed above the plurality of semiconductor multilayer film segments, the substrate defining a groove.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: February 27, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Yukitoshi Marutani
  • Patent number: 11915933
    Abstract: A manufacturing method of a semiconductor structure is disclosed, which includes: an initial structure is provided; a filling layer covering a spacer is formed on the initial structure; a filling layer with a first preset thickness is removed at a high first etching rate through a first etching process, then a filling layer with a second preset thickness is removed at a low second etching rate through a second etching process, and the partial spacer is exposed; and the filling layer and the spacer are patterned.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 27, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang Wan, Tao Liu, Sen Li
  • Patent number: 11916059
    Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection lay
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Stefan Pompl, Damian Sojka, Katharina Umminger
  • Patent number: 11908904
    Abstract: A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Sylvain Leomant, Thomas Feil, Yulia Polak, Maximilian Roesch
  • Patent number: 11908840
    Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Stephen St. Germain, Yusheng Lin
  • Patent number: 11901272
    Abstract: A semiconductor module includes a ceramic board, a circuit pattern metal plate on a principal surface of the ceramic board, and an external connection terminal including a bonding portion and a conductive portion. The metal plate includes a bonding area at a first surface thereof, and a stress relaxation portion disposed within the bonding area. The bonding portion has a bonding surface, and an edge that is located at a position overlapping an area in which the stress relaxation portion is disposed in a plan view. A solder is disposed between the bonding surface and the bonding area, to bond the external connection terminal to the circuit pattern metal plate.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 13, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshinori Uezato