Abstract: In some implementations of the invention, a silicon dioxide (SiO2) insulating layer added between islands of a top YBCO layer of a Josephson Junction isolates a contact layer from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, a SiO2 insulating layer added between islands of a bottom YBCO layer of adjacent Josephson Junctions isolates the contact layer or other components from YBCO (or other conductive components) in the Josephson Junction. In some implementations of the invention, an etch stop layer may be deposited over the islands of the top YBCO layer prior to adding the SiO2 insulating layer. This etch stop layer protects the top YBCO layer during the adding of the SiO2 insulating layer and during subsequent formation of a via through the SiO2 to the etch stop layer.

Abstract: A thin film transistor includes: a substrate; a gate electrode; an active layer including a first active pattern and a second active pattern, where the first active pattern includes a first active sub-pattern, the first active sub-pattern comprises a first active region and a first source-drain contact region, the first source-drain contact region is connected to the second active pattern through the first active region, the first active pattern includes a material of at least one of a metal oxide semiconductor, low-temperature polycrystalline silicon, and amorphous silicon, and the second active pattern includes a material of a semiconductor carbon nanotube; a source electrode and a drain electrode spaced apart from each other and connected to the active layer; and a passivation layer on a side of the second active pattern distal to the substrate. A method for manufacturing the thin film transistor and a circuit are further provided.

Abstract: A display device comprises a base substrate which is a base substrate having a display area and a non-display area positioned around the display area defined therein, and includes a substrate connection electrode penetrating the base substrate in the thickness direction, an etching stopper which is disposed on a first surface of the base substrate and that covers the substrate connection electrode, and a first pad disposed on a second surface opposite to the first surface of the base substrate and disposed overlapping a substrate through hole, wherein the substrate connection electrode is disposed in the display area, the substrate connection electrode is electrically connected to the etching stopper and the first pad, the etching stopper is electrically connected to the first pad through the substrate connection electrode, and the etching stopper includes a conductive material.

Abstract: Provided is a technology that enables reliable transfer of signal electric charges. This photodetection device includes a semiconductor layer having a first surface and a second surface located on opposite sides of the semiconductor layer in a thickness direction, a photoelectric conversion part provided in the semiconductor layer, first and second electric charge retaining parts provided adjacent to the first surface of the semiconductor layer, a first transfer transistor that transfers signal electric charges generated by photoelectric conversion in the photoelectric conversion part to the first electric charge retaining part, and a second transfer transistor that transfers the signal electric charges transferred by the first transfer transistor and retained in the first electric charge retaining part to the second electric charge retaining part.

Abstract: A semiconductor layout structure includes: active layers, each active layer including a first active area and a second active area arranged adjacent to the first active area, the first active area including first transistor areas spaced apart from each other, the second active area including second transistor areas spaced apart from each other; and gate layers, each gate layer being arranged above a respective active layer, and including at least one first gate structure extending along a first direction, and second gate structures spaced apart from each other in the first direction, and the at least one first gate structure and the second gate structures being arranged adjacent to each other, the at least one first gate structure corresponding to the first transistor areas, and each second gate structure corresponding to a second transistor area.

Abstract: A semiconductor encapsulation method, comprising: forming a protection layer on a front side of a chip to be encapsulated; arranging said chip, with the protection layer being formed on the front side thereof, on a carrier plate, wherein the front side of said chip faces upwards and a back side thereof faces the carrier plate; and encapsulating, on the carrier plate, said chip and the protection layer to form a plastic encapsulation layer. Further provided is a semiconductor encapsulation structure.

Abstract: A first-tier capacitor assembly is formed, which includes a first alternating layer stack embedded within a first substrate and including at least two first metallic electrode layers interlaced with at least one first node dielectric layer, and first metallic bonding pads located on a first front surface. A second-tier capacitor assembly is formed, which includes a second alternating layer stack embedded within a second substrate and including at least two second metallic electrode layers interlaced with at least one second node dielectric layers, and second metallic bonding pads located on a second backside surface. The second metallic bonding pads are bonded to the first metallic bonding pads such that each of the at least two first metallic electrode layers contacts a respective one of the at least two second metallic electrode layers. A capacitor with increased capacitance is provided.

Abstract: A method for physically unclonable function through gate height tuning is provided in the present invention, including steps of forming a high-k dielectric layer and a dummy silicon layer on a semiconductor substrate, removing the dummy silicon layer, forming a work function layer and a metal filling layer on the high-k dielectric layer, and performing a CMP process to remove the metal filling layer, so as to form metal gates with heights lower than a critical gate height, and using the metal gates to manufacture PIO pairs in an internal bias generator. Since the height of metal gates is lower than the critical gate height, a local threshold voltage mismatching of the programmed I/O (PIO) pairs becomes larger, so as to achieve random code generation in physically unclonable function (PUF).

Abstract: Display structures and methods of assembly are described. In an embodiment, a display structure includes a display panel including a pattern of trenches extending at least partially through a backplane of the display panel, without extending past a matrix of LEDs in an overlying emission layer stack. The plurality of trenches can be formed in 2D to facilitate bending of the display panel into a 3D film curvature.

Abstract: A display substrate is provided. The display substrate includes: a base substrate; a light-emitting unit layer arranged on the base substrate, wherein the light-emitting unit layer includes a plurality of light-emitting units respectively emitting light of a plurality of colors; and a light modulation layer located on a side of the light-emitting unit layer away from the base substrate, and configured to transmit a part of the light emitted from the plurality of light-emitting units and reflect the other part of the light emitted from the plurality of light-emitting units; wherein the light modulation layer is configured such that a reflectivity of the light modulation layer to light in a first wavelength range is greater than that of the light modulation layer to light outside the first wavelength range, and the first wavelength range is within a wavelength range of visible light and is 500 nm or more.

Abstract: A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, one or more through holes extending through the upper substrate in a thickness-wise direction, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin covering the upper surface of the upper substrate and filling the through holes.

Abstract: A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

Abstract: A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.

Abstract: A novel semiconductor device is provided. A memory string extends in a Z direction. The memory string achieves high-speed operation by using an oxide semiconductor for a semiconductor layer. The memory string includes a MONOS memory cell. A tunnel layer is provided on a control gate side, and a block layer is provided on a semiconductor side. During erase operation, a hole is injected into a charge accumulation layer from the control gate side.

Abstract: A light-emitting device of an embodiment of the present disclosure includes: an insulating layer having a first surface and a second surface that are opposed to each other; multiple columnar structures each including a columnar crystalline structure of a first electrically-conductive type erected in a direction perpendicular to the first surface of the insulating layer, and an active layer and a semiconductor layer of a second electrically-conductive type that are stacked in this order on a side surface and a top surface of the columnar crystalline structure; and a light-blocking member provided between the multiple columnar structures and having an inclined surface of less than 90° relative to the first surface.

Abstract: Embodiments of the present application provide an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a substrate and a Demux circuit disposed on the substrate, wherein the Demux circuit includes a first gate, a second gate, a first active layer, a second active layer, a first source, a second source, the first drain, and the second drain. The embodiments of the present application set the first gate and the second gate to be stacked in a direction perpendicular to the substrate, and the first active layer and the second active layer are set to be stacked in the direction perpendicular to the substrate, which can significantly reduce the occupied area of the Demux circuit in the horizontal direction.

Abstract: A circuit device includes: a first substrate having a first barrier layer; a second substrate having a second barrier layer; a first conductive portion arranged over the first barrier layer; a second conductive portion arranged over the second barrier layer; a first expanding pad arranged on the first conductive portion and including a first contact area greater than that of the first conductive portion; and a second expanding pad bonded to the first expanding pad, arranged on the second conductive portion and including a second expanded contact area greater than that of the second conductive portion. The first barrier layer and the second barrier layer include aluminum fluoride.

Abstract: A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.

Abstract: A substrate includes: a first printed circuit board layer including a first insulating layer and a first wiring layer, disposed on a lower surface of the first insulating layer; a second wiring layer, disposed on an upper surface of the first insulating layer; a bridge disposed above the first printed circuit board layer and including circuit wirings; a first bridge insulating layer and a second bridge insulating layer, disposed in the bridge and on which the circuit wirings are disposed, respectively; and a second printed circuit board layer including a second insulating layer surrounding side surfaces of the bridge and covering the first insulating layer and the second wiring layer. A first stacking direction in which the first insulating layer and the second insulating layer are stacked and a second stacking direction in which the first bridge insulating layer and the second bridge insulating layer are stacked are different.

Abstract: A second gate electrode is adjacent, in a Y direction, to a first tip of a semiconductor layer in a first active region such that a protruding distance of a second tip of the second gate electrode protruded, in a X direction, from the semiconductor layer in the first active region is greater than or equal to 0. Also, the first tip of the semiconductor layer in the first active region is covered with a second sidewall spacer. Further, a first epitaxial layer and the second gate electrode are electrically connected to each other via a first shared contact plug formed so as to across the first epitaxial layer, the second sidewall spacer and the second gate electrode.