Patents Examined by Eugene Lee
  • Patent number: 10204889
    Abstract: A package structure includes a semiconductor device, a first dielectric layer, a redistribution line and a conductive bump. The first dielectric layer is over the semiconductor device and has first and second openings on opposite surfaces of the first dielectric layer, wherein the first and second openings taper in substantially opposite direction. The redistribution line is partially in the first opening of the first dielectric layer and electrically connected to the semiconductor device. The conductive bump is partially embeddedly retained in the second opening and electrically connected to the redistribution line.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 10199269
    Abstract: A conductive structure includes a substrate including a first dielectric layer formed thereon, at least a first opening formed in the first dielectric layer, a low resistive layer formed in the opening, and a first metal bulk formed on the lower resistive layer in the opening. The first metal bulk directly contacts a surface of the first low resistive layer. The low resistive layer includes a carbonitride of a first metal material, and the first metal bulk includes the first metal material.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Han Chen, Yen-Tsai Yi, Chun-Chieh Chiu, Min-Chuan Tsai, Wei-Chuan Tsai, Hsin-Fu Huang
  • Patent number: 10199485
    Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
  • Patent number: 10199338
    Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Taku Kanaoka, Masashi Sahara, Yoshio Fukayama, Yutaro Ebata, Kazuhisa Higuchi, Koji Fujishima
  • Patent number: 10192904
    Abstract: A manufacturing method of an array substrate, including: forming a pattern layer including a pixel electrode, and a pattern layer including a gate electrode and a gate line on a base substrate; on the substrate with the pattern layer including the gate electrode and the gate line formed thereon, forming a gate insulating layer, a pattern layer at least including a metal oxide semiconductor active layer and a pattern layer at least including an etch stop layer; wherein, a first via hole for exposing the pixel electrode is formed over the pixel electrode; on the substrate with the etch stop layer formed thereon, forming a pattern layer including a source electrode, a drain electrode and a data line; wherein, the source electrode and the drain electrode each contact a metal oxide semiconductor active layer, and the drain electrode is electrically connected to the pixel electrode through the first via hole.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: January 29, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventor: Xiang Liu
  • Patent number: 10192924
    Abstract: An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 29, 2019
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Suguru Saito, Kaoru Koike
  • Patent number: 10192879
    Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10181446
    Abstract: The present technology relates to a camera module capable of reducing the number of steps in the manufacturing process and reducing a black spot failure, a method for manufacturing the camera module, an imaging apparatus, and an electronic instrument. A frame and the rigid flexible substrate are adhered to each other by adhesive formed of thermosetting resin applied on an abutment surface excluding a portion of a range including a bonding section with the FPC drawer unit, thereby forming a vent hole in a site where adhesive has not been applied. At this time, the air of the space between the frame and the rigid flexible substrate is expanded by the heat and discharged from the vent hole.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: January 15, 2019
    Assignee: SONY CORPORATION
    Inventors: Eiichiro Dobashi, Takahiro Wakabayashi
  • Patent number: 10176991
    Abstract: High-quality, single-crystalline silicon-germanium (Si(1-x)Gex) having a high germanium content is provided. Layers of the high-quality, single-crystalline silicon-germanium can be grown to high sub-critical thicknesses and then released from their growth substrates to provide Si(1-x)Gex films without lattice mismatch-induced misfit dislocations or a mosaic distribution of crystallographic orientations.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 8, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Max G. Lagally, Thomas Francis Kuech, Yingxin Guan, Shelley A. Scott, Abhishek Bhat, Xiaorui Cui
  • Patent number: 10170563
    Abstract: This invention discloses a gallium nitride based semiconductor power device disposed in a semiconductor substrate. The power device comprises a termination area disposed at a peripheral area of the semiconductor power device comprises a termination structure having at least a guard ring disposed in a trench filled with doped gallium-based epitaxial layer therein.
    Type: Grant
    Filed: February 9, 2013
    Date of Patent: January 1, 2019
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Tinggang Zhu
  • Patent number: 10163627
    Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying Lee, Shao-Ming Yu
  • Patent number: 10157939
    Abstract: An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: December 18, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10158022
    Abstract: A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second semiconductor layer includes a recessed portion, the air gap is located in the recessed portion, and the recessed portion has an upwardly-opening acute angle in the range from about 10° to about 55°. The air gap may prevent current leakage. A FinFET device may be manufactured by first recessing and then epitaxially re-growing a source/drain fin, with the regrowth starting over a tubular air gap.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: December 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Sheng-Hsu Liu, Jhen-cyuan Li, Chih-Chung Chen, Man-Ling Lu, Chung-Min Tsai, Yi-Wei Chen
  • Patent number: 10147853
    Abstract: Emitter packages are disclosed having a thixotropic agent or material, with the encapsulant exhibiting significant reduction of thixotropic agent scattering. The packages exhibit a corresponding reduction or elimination of encapsulant clouding and increased package emission efficiency. This allows for the thixotropic agents to be included in the encapsulant to alter certain properties (e.g. mechanical or thermal) while not significantly altering the optical properties of the encapsulant. One embodiment of a light emitting diode (LED) package according to the present invention comprises an LED chip with an encapsulant over the LED chip. The encapsulant has an encapsulant refractive index and also has a thixotropic material with a refractive index that is substantially the same as the encapsulant refractive index.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 4, 2018
    Assignee: CREE, INC.
    Inventors: Bernd Keller, Theodore Lowes
  • Patent number: 10141261
    Abstract: A method for manufacturing of a device including a first substrate including a plurality of sets of nanostructures arranged on the first substrate, wherein each of the sets of nanostructures is individually electrically addressable, the method including the steps of: providing a substrate having a first face, the substrate having an insulating layer including an insulating material arranged on the first face of the substrate forming an interface between the insulating layer and the substrate; providing a plurality of stacks on the first substrate, wherein each stack includes a first conductive layer and a second conductive layer; heating the first substrate having the plurality of stacks arranged thereon in a reducing atmosphere to enable formation of nanostructures on the second conductive material; heating the first substrate having the plurality of stacks arranged thereon in an atmosphere such that nanostructures are formed on the second layer.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: November 27, 2018
    Inventor: Waqas Khalid
  • Patent number: 10141417
    Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.
    Type: Grant
    Filed: March 5, 2016
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Hsiung Tsai, Kuo-Feng Yu, Chien-Tai Chan, Ziwei Fang, Kei-Wei Chen, Huai-Tei Yang
  • Patent number: 10134672
    Abstract: A semiconductor storage device includes a substrate, a stack of first insulating layers and conductive layers that are alternately formed on the substrate in a memory region and a peripheral region and electrically insulated from each other, a second insulating layer covering the stack of the first insulating layers and the conductive layers in the peripheral region, and a plurality of contact wirings formed in the peripheral region, each contact wiring extending from an upper surface of the second insulating layer towards the substrate and electrically connected to a corresponding one of the conductive layers. In the peripheral region, each conductive layer has an extended portion that covers side and upper surfaces of an end portion of a first insulating layer that is formed immediately thereabove, and each contact wiring is in direct contact with the extended portion of the corresponding conductive layer.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Takuya Inatsuka
  • Patent number: 10128117
    Abstract: A semiconductor device may include the following elements: a first doped region; a second doped region, which contacts the first doped region; a third doped region, which contacts the first doped region; a first dielectric layer, which contacts the above-mentioned doped regions; a first gate member, which is conductive and comprises a first gate portion, a second gate portion, and a third gate portion, wherein the first gate portion contacts the first dielectric layer, wherein the second gate portion is positioned between the first gate portion and the third gate portion, and wherein a width of the second portion is unequal to a width of the third gate portion; a doped portion, which is positioned between the third gate portion and the third doped region; a second gate member; and a second dielectric layer, which is positioned between the third gate portion and the second gate member.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: November 13, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Wenbo Wang, Hanming Wu
  • Patent number: 10121784
    Abstract: A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: November 6, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Junichi Nita, Kazutaka Suzuki, Takahiro Korenari, Yoshimasa Uchinuma
  • Patent number: 10121949
    Abstract: A light emitting device includes a resin molded body, which includes a front surface having an opening, a bottom surface opposite to the opening a front-rear direction of the light emitting device, and first and second wall portions extending from the bottom surface to the front surface. A first lead includes a first bottom portion provided on the bottom surface, first and second side portions provided in the first and second wall portions, respectively. A second lead include a second bottom portion provided on the bottom surface apart from the first lead to provide a first resin region, third and fourth side portions provided in the first and second wall portions apart from the first lead to provide second and third resin regions, respectively. The first resin region is provided between the second resin region and the third resin region viewed in the front-rear direction.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 6, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Takeshi Morikawa