Patents Examined by Eugene Lee
  • Patent number: 10297669
    Abstract: A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua Feng Chen, Shu-Hui Wang, Mu-Chi Chiang
  • Patent number: 10283700
    Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure also includes a top electrode formed over the MTJ cell; and a first sidewall spacer layer formed on a top surface of the MTJ cell and an outer sidewall surface of the top electrode.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Lin, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10276634
    Abstract: A semiconductor memory structure is provided. The semiconductor memory structure includes a bottom electrode formed over a substrate and a magnetic tunneling junction (MTJ) cell formed over the bottom electrode. The semiconductor memory structure includes a top electrode formed over the MTJ cell and a passivation layer surrounding the top electrode. The passivation layer has a recessed portion that is lower than a top surface of the top electrode. The semiconductor memory structure further includes a cap layer formed on the top electrode and the passivation layer, wherein the cap layer is formed in the recessed portion.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Lin, Yuan-Tai Tseng, Shih-Chang Liu
  • Patent number: 10276402
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: 10269919
    Abstract: A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the first and second devices includes a gate extending in a first direction, source/drain regions respectively formed on opposite first and second sides of the gate, dielectric spacers formed respectively on outer sidewalls of the gate on the first side and the second side, and conductive spacers serving contacts to the source/drain regions and formed respectively on outer sidewalls of the respective gate spacers. A second direction from the source/drain region on the first side to the source/drain region on the second side crosses the first direction.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Haizhou Yin
  • Patent number: 10270013
    Abstract: In embodiments of the invention, a light emitting device includes a semiconductor structure including a light emitting layer disposed between an n-type region and a p-type region. A first wavelength converting layer is disposed in a path of light emitted by the light emitting layer. The first wavelength converting layer may be a wavelength converting ceramic. A second wavelength converting layer is fused to the first wavelength converting layer. The second wavelength converting layer may be a wavelength converting material disposed in glass.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 23, 2019
    Assignee: LUMILEDS LLC
    Inventors: April Dawn Schricker, Oleg Borisovich Shchekin, Han Ho Choi, Peter Josef Schmidt
  • Patent number: 10262993
    Abstract: A semiconductor device includes a first transistor structure including a first transistor body region of a first conductivity type located within a semiconductor substrate. At least part of the first transistor body region is located between a first source/drain region of the first transistor structure and a second source/drain region of the first transistor structure. The semiconductor device includes a second transistor structure including a second transistor body region of a second conductivity type located within the semiconductor substrate. At least part of the second transistor body region is located between a first source/drain region of the second transistor structure and a second source/drain region of the second transistor structure. At least part of the second source/drain region of the second transistor structure is located between a doping region comprising the second source/drain region of the first transistor structure and the second transistor body region.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 16, 2019
    Assignee: Infineon Technologies AG
    Inventors: Marten Müller, Hans-Günter Eckel
  • Patent number: 10249508
    Abstract: A method for manufacturing a semiconductor device includes forming a first semiconductor layer on a semiconductor substrate, forming a first insulator layer on the first semiconductor layer, forming a patterned second semiconductor layer on the first insulator layer, the patterned second semiconductor layer having an actual thickness greater than a target thickness and exposing a portion of the first insulator layer; forming a second insulator layer as a spacer on the exposed portion of the first insulator layer, and performing an etching process on the patterned second semiconductor layer until the second semiconductor layer has the target thickness and concurrently removing the second insulator layer. The method can eliminate capillary etching of the spacer in a subsequent removal of the first insulator layer.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 2, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Xianchao Wang
  • Patent number: 10249551
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10243000
    Abstract: Provided are a 3-dimensional non-volatile memory device and a method of fabricating the same. The 3-dimensional non-volatile memory device may include a substrate; semiconductor pillars, which are arranged at a certain interval in a first direction and a second direction different from the first direction; a string isolation film, which is arranged between the semiconductor pillars arranged in the first direction among the semiconductor pillars and extends in the first direction and a third direction vertical to the main surface of the substrate; first sub-electrodes repeatedly stacked on the substrate in the third direction; second sub-electrodes, which are electrically isolated from the first sub-electrodes by the string isolation film, and are repeatedly stacked on the substrate in the third direction; and information storage films including a first information storage film and a second information storage film.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 26, 2019
    Assignee: UNIVERSITY-INDUSTRY FOUNDATION (UIF), YONSEI UNIVERSITY
    Inventors: Hyun Chul Sohn, Hee Do Na, Young Mo Kim
  • Patent number: 10243003
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10242867
    Abstract: A method of fabricating a FinFET device includes forming contact openings for source/drain contacts prior to performing a replacement metal gate (RMG) module. Etch selective metals are used to form source/drain contacts and gate contacts optionally within active device regions using a block and recess technique.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: March 26, 2019
    Assignee: GLOBALFOUNDARIES INC.
    Inventors: Guillaume Bouche, Vimal Kamineni
  • Patent number: 10236237
    Abstract: Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor includes: a collector layer that has a long-side direction and a short-side direction in a plan view, in which the short-side direction is parallel to crystal orientation [011], a cross-section perpendicular to the short-side direction has an inverted mesa shape, and a cross-section perpendicular to the long-side direction has a forward mesa shape; a base layer that is formed on the collector layer; a base electrode that is formed on the base layer; and a base line that is connected to the base electrode and that is drawn out from an end in the short-side direction of the collector layer to the outside of the collector layer in a plan view.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Kenji Sasaki
  • Patent number: 10236384
    Abstract: A finFET structure, and method of forming such structure, in which a germanium enriched nanowire is located in the channel region of the FET, while simultaneously having silicon-germanium fin in the source/drain region of the finFET.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Pouya Hashemi, Ali Khakifirooz, John A. Ott, Alexander Reznicek
  • Patent number: 10236367
    Abstract: A device includes a substrate, a first well doped with dopants of a first conductivity type defined in the substrate, and a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the substrate adjacent the first well to define a PN junction. The second well includes a silicon alloy portion displaced from the PN junction. A collector region contacts one of the first or second wells and has a dopant concentration higher than its contacted well. An emitter region contacts the other of the first or second wells and is doped with dopants of the first or second conductivity type different than the first or second well contacted by the emitter region. A base region contacts the other of the first or second well and has a dopant concentration higher than the first or second well contacted by the base region.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jagar Singh, Shiv Kumar Mishra
  • Patent number: 10231324
    Abstract: Some novel features pertain to an integrated device that includes a first metal layer and a second metal layer. The first metal layer includes a first set of regions. The first set of regions includes a first netlist structure for a power distribution network (PDN) of the integrated device. The second metal layer includes a second set of regions. The second set of regions includes a second netlist structure of the PDN of the integrated device. In some implementations, the second metal layer further includes a third set of regions comprising the first netlist structure for the PDN of the integrated device. In some implementations, the first metal layer includes a third set of regions that includes a third netlist structure for the PDN of the integrated device. The third set of regions is non-overlapping with the first set of regions of the first metal layer.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: March 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ryan David Lane, Yue Li, Charles David Paynter, Ruey Kae Zang
  • Patent number: 10217688
    Abstract: An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and a heat-sink thermally coupled to the heat-spreader. The heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice. The heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor devices.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Standing
  • Patent number: 10217702
    Abstract: A semiconductor device includes a BGA package including first bumps. A first semiconductor die is mounted to the BGA package between the first bumps. The BGA package and first semiconductor die are mounted to a carrier. A first encapsulant is deposited over the carrier and around the BGA package and first semiconductor die. The carrier is removed to expose the first bumps and first semiconductor die. An interconnect structure is electrically connected to the first bumps and first semiconductor die. The BGA package further includes a substrate and a second semiconductor die mounted, and electrically connected, to the substrate. A second encapsulant is deposited over the second semiconductor die and substrate. The first bumps are formed over the substrate opposite the second semiconductor die. A warpage balance layer is formed over the BGA package.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: February 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen
  • Patent number: 10217856
    Abstract: A semiconductor device includes: a first base layer; a drain layer disposed on the back side surface of the first base layer; a second base layer formed on the surface of the first base layer; a source layer formed on the surface of the second base layer; a gate insulating film disposed on the surface of both the source layer and the second base layer; a gate electrode disposed on the gate insulating film; a column layer formed in the first base layer of the lower part of both the second base layer and the source layer by opposing the drain layer; a drain electrode disposed in the drain layer; and a source electrode disposed on both the source layer and the second base layer, wherein heavy particle irradiation is performed to the column layer to form a trap level locally.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: February 26, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Toshio Nakajima
  • Patent number: 10211069
    Abstract: An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: February 19, 2019
    Assignee: Intel Corporation
    Inventor: Tin Poay Chuah