Patents Examined by Eugene Lee
  • Patent number: 10115750
    Abstract: An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (BJTs) having opposite polarities. The first lateral BJT has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second lateral BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second lateral BJTs, the sensing structure, and the substrate on which they are formed comprise a monolithic structure.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Gordon, Tak H. Ning, Kenneth P. Rodbell, Jeng-Bang Yau
  • Patent number: 10107773
    Abstract: Capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics are disclosed. A capacitive based sensor is disposed over a first predetermined portion of a wafer that includes at least a first ceramic element providing protection for the final capacitive based sensor and self-aligned processing during its manufacturing.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: October 23, 2018
    Assignee: MEMS-Vision International Inc.
    Inventors: Mourad El-Gamal, Paul-Vahe Cicek, Frederic Nabki
  • Patent number: 10079261
    Abstract: An image sensor includes a plurality of photodiodes and a floating diffusion disposed in a semiconductor material. The image sensor also includes a plurality of transfer gates coupled between the plurality of photodiodes and the floating diffusion to transfer the image charge generated in the plurality of photodiodes into the floating diffusion. Peripheral circuitry is disposed proximate to the plurality of photodiodes and coupled to receive the image charge from the plurality of photodiodes. A shallow trench isolation structure is laterally disposed, at least in part, between the plurality of photodiodes and the peripheral circuitry to prevent electrical crosstalk between the plurality of photodiodes and the peripheral circuitry. The peripheral circuitry includes one or more transistors including a source electrode and a drain electrode that are raised above a surface of the semiconductor material.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: September 18, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Qin Wang, Bill Phan, Sing-Chung Hu, Gang Chen
  • Patent number: 10068883
    Abstract: An optical coupling device includes a first receiving chip having a first region on one end and a second region on another end side. A first emitting chip is disposed on the first region. A second receiving chip has a third region on one end and a fourth region on another end. A second emitting chip is disposed on the fourth region. The first and third regions are adjacent, and the second and fourth regions are adjacent. A first connection portion is disposed on the second region and is electrically connected to the second light emitting chip through a bonding wire. A second connection portion is disposed in the third region and is electrically connected to the first light emitting chip through a bonding wire.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: September 4, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuta Kugiyama, Hisami Saito
  • Patent number: 10068855
    Abstract: A semiconductor package includes a frame including a through-hole, an electronic component disposed in the through-hole, a redistribution portion disposed below the frame and the electronic component, a metal layer disposed on an inner surface of the frame, and a conductive layer disposed between the metal layer and the electronic component, and covering the frame and the electronic component.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 4, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Thomas A. Kim, Kyu Bum Han, Kwan Hoo Son
  • Patent number: 10043676
    Abstract: A local thinning process is employed on the backside of a semiconductor substrate such as a wafer in order to improve the thermal performance of the electronic device built on or in the front side of the wafer.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: August 7, 2018
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Sanfilippo Carmelo, Luigi Merlin, Isabella Para, Giovanni Richieri
  • Patent number: 10038098
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 31, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10032924
    Abstract: An apparatus is provided that includes a substrate and source and drain regions within an annealed active layer having resulted from an annealing of an active layer comprising metal-oxide and formed on the substrate, and an impermeable layer over the source and drain regions of the annealed active layer, wherein the annealing resulting in the annealed active layer was performed with the impermeable layer over portions of the active layer corresponding to the source and drain regions, thereby resulting in a reduction of a resistivity of the source and drain regions of the annealed active layer relative to the active layer. In another aspect, a junctionless transistor is provided wherein the entire active area has a low resistivity based on annealing of an active layer including metal oxide while uncovered or at least partially covered with layers of various gas permeability under oxidizing or non-oxidizing conditions.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: July 24, 2018
    Assignee: THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Lei Lu, Man Wong, Hoi Sing Kwok
  • Patent number: 10026773
    Abstract: An image pickup device according to the present disclosure includes a first pixel and a second pixel each including a photodetection section and a light condensing section, the photodetection section including a photoelectric conversion element, the light condensing section condensing incident light toward the photodetection section, the first pixel and the second pixel being adjacent to each other and each having a step part on a photodetection surface of the photodetection section, in which at least a part of a wall surface of the step part is covered with a first light shielding section.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: July 17, 2018
    Assignee: Sony Corporation
    Inventors: Takeshi Yanagita, Suguru Saito, Kaoru Koike
  • Patent number: 10020408
    Abstract: Architecture of the light-to-electricity converter characterized in that the system of amorphized nanograins, preferentially nanograins of amorphized silicon, of any shape are optimally spread within the crystalline host material, preferentially crystalline silicon that are wrapped around with a metamaterial seg-matter nanolayer, characterized by secondary generation centers, called segtons, that are conditioned around divacancies and disposed entirely or only partly within the volume of the emitter, this volume being limited at each end by a nanomembrane assuming the appropriate exploitation of the lower-energy secondary generation through the giant photoconversion involving hot electrons, segtons, and seg-matter.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: July 10, 2018
    Assignee: SEGTON ADVANCED TECHNOLOGY
    Inventors: Zbigniew Kuznicki, Patrick Meyrueis
  • Patent number: 10020407
    Abstract: This cooling mechanism for a surface-mounted-type photoelectric conversion element is provided on a circuit board to which a surface-mounted-type photoelectric conversion element, which has a signal terminal that is connected to inner wiring and a terminal for fixation that is not connected to the inner wiring on a back surface thereof, is mounted, the cooling mechanism has a front-surface-side copper foil pattern to which the terminal for fixation is connected, a back-surface-side copper foil pattern, and a through-hole via which connects the copper foil patterns, a cooling member which is fixed to the circuit board so as to have contact with the back-surface-side copper foil pattern, and which cools the back-surface-side copper foil pattern.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: July 10, 2018
    Assignee: OLYMPUS CORPORATION
    Inventor: Shogo Usui
  • Patent number: 10020434
    Abstract: A surface-mountable optoelectronic component has a radiation passage face, an optoelectronic semiconductor chip and a chip carrier. A cavity is formed in the chip carrier and the semiconductor chip is arranged in the cavity. A molding surrounds the chip carrier at least in places. The chip carrier extends completely through the molding in a vertical direction perpendicular to the radiation passage face.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: July 10, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Michael Zitzlsperger, Harald Jaeger
  • Patent number: 10014446
    Abstract: A chip substrate includes conductive layers, an insulation layer configured to electrically isolate the conductive layers, and a cavity composed of a groove formed at a predetermined depth in a region including the insulation layer. One side of the cavity includes a first surface and a second surface continuously extending from the first surface, the first surface is formed to vertically extend from a lower portion of the cavity and the second surface is formed so as to have the same slope as the other side of the cavity, whereby the distance between one side of the lower portion of the cavity and the insulation layer is increased.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: July 3, 2018
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Tae Hwan Song
  • Patent number: 10008650
    Abstract: A semiconductor light-emitting device includes a lead frame, a semiconductor light-emitting element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: June 26, 2018
    Assignee: ROHM CO., LTD.
    Inventor: Masahiko Kobayakawa
  • Patent number: 10008626
    Abstract: An optical coupling device includes a light-emitting element, a light-receiving element that faces the light-emitting element, a lead frame that has a first surface on which the light-emitting element is provided and a second surface facing the first surface, a first covering material that covers the light-emitting element, a second covering material that covers the first covering material, the light-receiving element, and the lead frame, and a third covering material that covers the second covering material. At least one of first bonding strength between the second covering material and the third covering material and second bonding strength between the second covering material and the second surface is lower than third bonding strength between the first covering material and the second covering material.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 26, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuya Muranaka
  • Patent number: 9991403
    Abstract: An improved optoelectronic device is described, which employs optically responsive nanoparticles and utilises a non-radiative energy transfer mechanism. The nanoparticles are disposed on the sidewalls of one or more cavities, which extend from the surface of the device through the electronic structure and penetrate the energy transfer region. The nanoparticles are located in close spatial proximity to an energy transfer region, whereby energy is transferred non-radiatively to or from the electronic structure through non-contact dipole-dipole interaction. According to the mode of operation, the device can absorb light energy received from the device surface via the cavity and then transfer this non-radiatively or can transfer energy non-radiatively and then emit light energy towards the surface of the device via the cavity. As such, the deice finds application in light emitting devices, photovoltaic (solar) cells, displays, photodetectors, lasers and single photon devices.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: June 5, 2018
    Inventors: Martin David Brian Charlton, Pavlos Lagoudakis, Soontorn Chanyawadee
  • Patent number: 9991183
    Abstract: A semiconductor component includes an inner semiconductor component housing and an outer semiconductor component housing. The inner semiconductor component housing includes a semiconductor chip, a first plastic housing composition and first housing contact surfaces. At least side faces of the semiconductor chip are embedded in the first plastic housing composition and the first housing contact surfaces are free of the first plastic housing composition and include a first arrangement. The outer semiconductor component housing includes a second plastic housing composition and second housing contact surfaces which include a second arrangement. The inner semiconductor component housing is situated within the outer semiconductor component housing and is embedded in the second plastic housing composition. At least one of the first housing contact surfaces is electrically connected with at least one of the second housing contact surfaces.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Josef Hoeglauer, Teck Sim Lee, Ralf Otremba, Klaus Schiess, Xaver Schloegel, Juergen Schredl
  • Patent number: 9985165
    Abstract: An optical coupling device includes a primary conductive plate, a light-emitting part, a secondary conductive plate, a light-receiving part, and a first conductive part. The light-emitting part is located on the primary conductive plate, converts an electrical signal to light, and emits the light. The secondary conductive plate is spaced apart from the primary conductive plate, and faces the light-emitting part. The light-receiving part is disposed on the secondary conductive plate to face the light-emitting part, and converts light from the light-emitting part to an electrical signal. The first conductive part is disposed at a side facing the light-emitting part, and has a point on which an electric field generated by a potential difference between the primary conductive plate and the secondary conductive plate is concentrated.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: May 29, 2018
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yuichi Niimura
  • Patent number: 9978725
    Abstract: Provided is an LED lamp using a nano-scale LED electrode assembly. The LED lamp using the nano-scale LED electrode assembly may solve limitations in which, when a nano-scale LED device according to the related art stands up and is three-dimensionally coupled to an electrode, it is difficult to allow the nano-scale LED device to stand up, and when the nano-scale LED devices are coupled to one-to-one correspond to electrodes different from each other, product quality is deteriorated. Thus, the nano-scale LED device having a nano unit may be connected to the two electrodes different from each other without causing defects, and light extraction efficiency may be improved due to the directivity of the nano-scale LED devices connected to the electrodes.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: May 22, 2018
    Assignee: PSI CO., LTD.
    Inventor: Young Rag Do
  • Patent number: 9978918
    Abstract: A method can be used for producing an optoelectronic device. A first leadframe section with a component is provided. The component is designed to emit electromagnetic radiation on an emission side. The emission side faces away from the carrier. A second leadframe section is provided. In a first method step the component and the two leadframe sections are encapsulated with a first potting material in such a way that the component and the leadframe sections are embedded into a potting body, but wherein at least part of the emission area of the component remains free of the first potting material and a cutout is formed in the potting body at least above the emission area of the component. In a second method step a second potting material is molded into the cutout of the potting body, such that the emission side of the component is covered with the second potting material.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 22, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Zitzlsperger, Tobias Gebuhr, Thomas Schwarz