Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Abstract: Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. Localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.

Abstract: A method of fabricating a semiconductor device includes forming a metal film including Cu on a substrate, forming a protective film on the metal film, forming a hard mask including TaOx, where x is 2.0 to 2.5, on the protective film, forming a hard mask pattern by patterning the hard mask, and forming a metal wiring by patterning the metal film, using the hard mask pattern as an etching mask.

Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include forming a first cut portion from a conductive foil. The method can also include aligning the first cut portion to a first doped region of a first semiconductor substrate. The method can include bonding the first cut portion to the first doped region of the first semiconductor substrate. The method can also include aligning and bonding a plurality of cut portions of the conductive foil to a plurality of semiconductor substrates.

Abstract: An electronic device is disclosed, which comprises: a first substrate; an adhesion layer disposed on the first substrate and comprising a condensation product of silane or derivatives thereof; an inorganic layer disposed on the adhesion layer; and an active unit disposed on the inorganic layer. In addition, the present disclosure also provides a method for manufacturing the aforementioned electronic device.

Abstract: A method for fabricating a WLCSP device includes receiving a MEMS cap wafer having a first radius, a MEMS device wafer having a second radius, and a CMOS substrate wafer having a third radius, wherein the first radius is smaller than the second radius, and wherein the second radius is smaller than the third radius, disposing the MEMS cap wafer approximately concentrically upon the MEMS device wafer, disposing the MEMS device wafer approximately concentrically upon the CMOS substrate wafer, disposing a spacer structure upon the MEMS device wafer, wherein the spacer structure comprises a plurality of proximity spacers disposed upon a proximity flag, wherein the plurality of proximity spacers are disposed upon the MEMS device wafer, disposing a mask layer in contact to the plurality of proximity spacers, above and substantially parallel to the MEMS cap wafer, and forming a pattern upon the MEMS cap wafer using the mask layer.

Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.

Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.

Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include placing conductive wires in a wire guide, where conductive wires are placed over a first semiconductor substrate having first doped regions and second doped regions. The method can include aligning the conductive wires over the first and second doped regions, where the wire guide aligns the conductive wires substantially parallel to the first and second doped regions. The method can include bonding the conductive wires to the first and second doped regions. The bonding can include applying a mechanical force to the semiconductor substrate via a roller or bonding head of the wire guide, where the wire guide inhibits lateral movement of the conductive wires during the bonding.

Abstract: A method of forming a plurality of semiconductor devices includes applying a tape material to a back side of a semiconductor device having a silicon layer on the back side and a circuitry layer on the front side, lasing with an infrared laser the silicon layer through the tape material, lasing with a second laser the circuitry layer, and expanding the tape material for form a plurality of semiconductor devices. The second layer may be an ultraviolet laser. The lasers may be irradiated in a pattern on the bottom side and the top side. The second layer may form a groove in the circuitry layer that does not penetrate the silicon layer. The infrared laser may cleave a portion of the silicon lattice of the silicon layer. A coating may be applied to the circuitry layer prior to being irradiated with the second laser.

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.

Abstract: Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

Abstract: A method for polymerizing a composition including hydridosilanes and subsequently using the polymers to produce silicon containing layers, comprising the following steps: a) providing a substrate; b) providing a composition including at least one hydridosilane that is dissolved in at least one organic and/or inorganic solvent, or including at least one hydridosilane that is already present in liquid form without solvent, wherein the hydridosilanes comprise at least one linear and/or one branched hydridosilane of the general formula SinH2n+2, where n?3, and/or a cyclic hydridosilane of the general formula SinH2n, where n?3; c) polymerizing the composition from step b) by way of acoustic cavitation; and d) coating the surface of the substrate with reaction products from step c).

Abstract: A method for forming gate cuts during RMG processing and the resulting device are provided. Embodiments include forming Si fins over a substrate; forming a STI layer over the substrate and recessed, exposing upper portions of the Si fins; forming polysilicon dummy gate electrodes perpendicular to the Si fins, separated by STI regions, on the upper portions of the Si fins and on the STI layer between the Si fins; forming a hardmask over the polysilicon dummy gate electrodes; etching through the hardmask and polysilicon dummy gate electrodes forming cavities between some of the Si fins; oxidizing polysilicon exposed on sides of the cavities and any residual polysilicon remaining at a bottom of one or more of the cavities; filling the cavities with SiN; removing the polysilicon dummy gate electrodes; and forming RMGs.

Abstract: A novel plasma process is introduced as an improvement over conventional plasma processes during formation of spacers for FinFET devices. Under this novel plasma process, an oxide layer is grown over sidewall materials and low energy plasma gas is used for the over-etching of the corner areas of the sidewalls. The oxide layer can effectively protect the sidewall materials during the over-etching by the low energy plasma gas and thus to reduce the aforementioned CD losses introduced by the low energy plasma gas. This improved low energy plasma etching technique can protect the fin structure from CD losses as compared to the conventional low energy plasma process, and also avoid damaging fin silicon structure with reduced Si losses as compared to the conventional high energy plasma process.

Abstract: An electro-optic apparatus includes an element substrate, a pixel region including a first and second pixel formed on the element substrate, a first terminal formed on the element substrate, a second terminal formed on the element substrate, located opposite of the pixel region with the first terminal being interposed between the pixel region and the second terminal, a first wiring extending from the first terminal included in a path for transmitting to the first pixel, a first signal having been input to the first terminal and a second wiring extending from the second terminal included in a path for transmitting to the second pixel, a second signal having been input to the second terminal. Further, a difference between a resistance of the path for transmitting the first and second signal is made smaller than a resistance difference due to a difference between a length of the first and second wiring.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

Abstract: Flash light is emitted from flash lamps to the surface of a semiconductor substrate on which a metal layer has been formed for one second or less to momentarily raise temperature on the surface of the semiconductor substrate including the metal layer and an impurity region to a processing temperature of 1000° C. or more. Heat treatment is performed by emitting flash light to the surface of the semiconductor substrate in a forming gas atmosphere containing hydrogen. By heating the surface of the semiconductor substrate to a high temperature in the forming gas atmosphere for an extremely short time period, contact resistance can be reduced without desorbing hydrogen taken in the vicinity of an interface of a gate oxide film for hydrogen termination.

Abstract: A composition for forming a silica layer including a silicon-containing polymer having a weight average molecular weight of about 20,000 to about 70,000 and a polydispersity index of about 5.0 to about 17.0 and a solvent; a silica layer manufactured using the same; and an electronic device including the silica layer.

Abstract: A laser annealing method that includes forming a second layer having through holes on a first layer, and radiating laser light with a wavelength of 3 ?m or greater to the first layer via the through holes.