Abstract: A method of fabricating high-k/metal gate semiconductor device by incorporating an enhanced annealing process is provided. The enhanced annealing process in accordance with the disclosure can be operated at relatively low temperature and high pressure and thus can improve the k value and repair the above-mentioned deficiencies of the HK layer. Under the enhanced annealing process in accordance with the disclosure, H+ can be diffused from the ammonia gas and to repair the broken bonds because of high pressure, while avoiding adversely impact the NiSi and implanted ions in the HK layer due to the low temperature. The enhanced annealing process in accordance with the disclosure can be performed between 300° C. to 500° C. at a pressure of 15-20 atm for 15 to 50 minutes in some embodiments.

Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

Abstract: A cobalt deposition process, including: volatilizing a cobalt precursor selected from among CCTBA, CCTMSA, and CCBTMSA, to form a precursor vapor; and contacting the precursor vapor with a substrate under vapor deposition conditions effective for depositing on the substrate (i) high purity, low resistivity cobalt or (ii) cobalt that is annealable by thermal annealing to form high purity, low resistivity cobalt. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms an electrode, capping layer, encapsulating layer, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel display, or solar panel.

Abstract: A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.

Abstract: This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching step, a SiC substrate in which at least the surface is formed from single crystal SiC, and which has been subjected to machining, is subjected to heat treatment under Si atmosphere to etch the surface of the SiC substrate. In the measurement step, the surface roughness or the residual stress of the SiC substrate which has been subjected to the etching step is measured. In the estimation step, the depth of latent scratches or the presence or absence of latent scratches in the SiC substrate before the etching step are estimated on the basis of the results obtained in the measurement step.

Abstract: A method for equalizing the thickness variation of a substrate stack which is comprised of a product substrate and a carrier substrate and which is connected in particular by means of an interconnect layer, by local application of local thickness peaks by means of an application apparatus which has at least one application unit. Furthermore this invention relates to a corresponding device.

Abstract: Embodiments of systems and methods for substrate thermal processing using a hot plate with a programmable array of lift devices for multi-bake process optimization are presented. In an embodiment, an apparatus includes a base with an upper surface configured to receive the substrate. The base may include at least one heater for heating the substrate while on or in the vicinity of the base, and a plurality of lift devices configured to selectively extend from the upper surface of the base to support the substrate above the base when extended, and allow the substrate to rest on the upper surface of the base when retracted, each lift device being actuated independently of the other lift devices by an actuating mechanism. Additionally, the apparatus may include a controller for controlling the plurality of actuating mechanisms.

Abstract: Provided is a method of manufacturing a mask including preparing a support plate, forming a light blocking layer on the support plate, curing a predetermined region of the light blocking layer, and removing other region of the light blocking layer, excluding the predetermined region.

Abstract: Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer and the resulting device are provided. Embodiments include providing a SOI structure having a substrate, BOX, device and metallization layers; bonding a handling layer to the metallization layer; removing the substrate; forming a passivation oxide layer over the BOX; forming first and second trenches through the passivation, BOX, and device layers down to the metallization layer; forming a third trench through the passivation layer and a portion of the BOX above a PA power cell region of the SOI structure, a thin portion of the BOX remaining; forming a first backside contact in the first trench; and forming a second backside contact in the second and third trenches and over a portion of the passivation oxide layer.

Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.

Abstract: An electro-optical device is capable of high quality images. An electro-optical device (200) includes a first capacitive element (491), a second capacitive element (492), and a third capacitive element (493). The first capacitive element (491) includes a first conductive film (408), a first part of a second conductive film (411), and a first dielectric film (410). The second capacitive element (492) includes a third conductive film (416), a second part of a fourth conductive film (418), and a second dielectric film (417). The third capacitive element (493) includes the third conductive film (416), a third part of the fourth conductive film (418), and the second dielectric film (417). Since a capacitive element that includes a large capacitance value is formed in a narrow region, even if the pixel becomes smaller as the definition is increased, it is possible to realize an excellent electro-optical device in which display defects are suppressed.

Abstract: An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.

Abstract: A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.

Abstract: A method for fabricating semiconductor device is disclosed. First, a first fin-shaped structure and a second fin-shaped structure are formed on a substrate, and a shallow trench isolation (STI) is formed around the first fin-shaped structure and the second fin-shaped structure, a patterned hard mask is formed on the STI. Next, part of the first fin-shaped structure and part of the second fin-shaped structure adjacent to two sides of the patterned hard mask are removed for forming a first recess and a second recess, and a dielectric material is formed into the first recess and the second recess.

Abstract: A production process for a device in which a first substrate and a second substrate are bonded to each other with bonding surfaces thereof mutually bonded and the second substrate has a through-hole, the production process including the steps of bonding the first substrate and the second substrate to each other with the presence of a non-bonding region formed by a recessed shape portion recessed from at least one of the bonding surface of the first substrate and the bonding surface of the second substrate; and causing at least a part of a portion of the second substrate corresponding to the non-bonding region to pass through.

Abstract: A solution contains a functional material for constituting a function layer, and a solvent. The solvent contains a high-boiling-point solvent composed of one or more solvent components having a boiling point of not less than 200° C. The high-boiling-point solvent has a viscosity of from 13 mPa·s to 25 mPa·s, inclusive, and a surface tension of from 33 mN/m to 37 mN/m, inclusive.

Abstract: A plasma generator, a plasma annealing device, a deposition crystallization apparatus and a plasma annealing process are disclosed. The plasma generator includes: a gas chamber; a gas intake member configured to introduce a gas into the gas chamber; a cathode and an anode that are configured to apply an electric field to the gas introduced into the gas chamber to ionize the gas into plasma; a cooling water circulation member configured to control a temperature of the plasma generator; and a plasma beam outlet disposed on a top face of the gas chamber. The plasma annealing device including the plasma generator can generate a plasma beam, which can be used in annealing to amorphous silicon and crystallize the amorphous silicon to polycrystalline silicon.

Abstract: In described examples, an embedded thermoelectric device is formed by forming isolation trenches in a substrate, concurrently between CMOS transistors and between thermoelectric elements of the embedded thermoelectric device. Dielectric material is formed in the isolation trenches to provide field oxide which laterally isolates the CMOS transistors and the thermoelectric elements. Germanium is implanted into the substrate in areas for the thermoelectric elements, and the substrate is subsequently annealed, to provide a germanium density of at least 0.10 atomic percent in the thermoelectric elements between the isolation trenches. The germanium may be implanted before the isolation trenches are formed, after the isolation trenches are formed and before the dielectric material is formed in the isolation trenches, and/or after the dielectric material is formed in the isolation trenches.

Abstract: A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to the first and second sacrificial mandrels. A filler material is deposited on the second hardmask. A first mask is formed on a portion of the second sacrificial mandrel. A first cavity and a second cavity are formed that expose portions of the second hardmask, and exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. Exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a trench in the insulator layer and the trench is filled with a conductive material.

Abstract: A laterally diffused metal oxide semiconductor device includes: a substrate (10); a buried layer region (32) in the substrate; a well region (34) on the buried layer region (32); a gate region on the well region; a source region (41) and a drain region (43) which are located at two sides of the gate region; and a super junction structure.