Abstract: Embodiments are directed to a method of forming features of a semiconductor device. The method includes forming a first feature including a first type of semiconductor material, which can be tensile or can have compressive strain. The method further includes forming an enclosure structure including a second type of semiconductor material, wherein the first feature includes first feature sidewall surfaces extending around a circumference of the first feature. The enclosure structure is adjacent at least a portion of the first feature sidewall surfaces and extends around the circumference of the first feature.

Abstract: Methods and systems for forming a layer from a fluid mixture on a web are provided. The system includes a fluid delivery apparatus for delivering the fluid mixture onto the web. The fluid delivery apparatus includes a cascade device and a chemical dispenser device. The system also includes a fluid stirring apparatus comprising at least one fan positioned over the web and configured to generate a flow pattern that stirs the fluid mixture on the web while the layer is being formed, without the at least one fan contacting the fluid mixture. The system further includes a fluid removal apparatus having a rinsing device and a suction device. The rinsing device is configured to dispense a rinsing fluid onto the web. The suction device is configured to remove by suction the rinsing fluid and a remaining portion of the fluid mixture remaining on the web after formation of the layer.

Abstract: In described examples, an integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming active areas which provide transistor active areas for an NMOS transistor and a PMOS transistor of the CMOS transistors and provide n-type thermoelectric elements and p-type thermoelectric elements of the embedded thermoelectric device. Stretch contacts with lateral aspect ratios greater than 4:1 are formed over the n-type thermoelectric elements and p-type thermoelectric elements to provide electrical and thermal connections through metal interconnects to a thermal node of the embedded thermoelectric device. The stretch contacts are formed by forming contact trenches in a dielectric layer, filling the contact trenches with contact metal and subsequently removing the contact metal from over the dielectric layer. The stretch contacts are formed concurrently with contacts to the NMOS and PMOS transistors.

Abstract: A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.

Abstract: A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.

Abstract: A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face the partition block, and first lines extending from the partition block to the first open region. A spacer is formed on sidewalls of the partition to define a second open region overlapping with the first open region and to include second lines on sidewalls of the first lines. The partition may be removed to open a third open region occupied by the partition block and spaces between the second lines. A target pattern is formed to include third lines filling the spaces between the second lines, a first pad block filling the second open region, and a second pad block filling the third open region. Each of the first and second pad blocks is separated into a plurality of pads.

Abstract: A method of forming a hard mask includes depositing step for depositing a titanium nitride film on a surface of a to-be-processed object; adsorbing step for adsorbing oxygen-containing molecules onto a surface of the titanium nitride film; and heating step for heating the titanium nitride film to a predetermined temperature.

Abstract: Flash light is emitted from flash lamps to the surface of a semiconductor substrate on which a metal layer has been formed for one second or less to momentarily raise temperature on the surface of the semiconductor substrate including the metal layer and an impurity region to a processing temperature of 1000° C. or more. Heat treatment is performed by emitting flash light to the surface of the semiconductor substrate in a forming gas atmosphere containing hydrogen. By heating the surface of the semiconductor substrate to a high temperature in the forming gas atmosphere for an extremely short time period, contact resistance can be reduced without desorbing hydrogen taken in the vicinity of an interface of a gate oxide film for hydrogen termination.

Abstract: Aspects of the methods and apparatus described herein relate to deposition of tungsten nucleation layers and other tungsten-containing films. Various embodiments of the methods involve exposing a substrate to alternating pulses of a tungsten precursor and a reducing agent at low chamber pressure to thereby deposit a tungsten-containing layer on the surface of the substrate. According to various embodiments, chamber pressure may be maintained at or below 10 Torr. In some embodiments, chamber pressure may be maintained at or below 7 Torr, or even lower, such as at or below 5 Torr. The methods may be implemented with a fluorine-containing tungsten precursor, but result in very low or undetectable amounts of fluorine in the deposited layer.

Abstract: The present invention discloses an array substrate, comprising: a substrate; peripheral lines provided in a peripheral region of the substrate; an insulation layer provided over the peripheral lines and comprising through holes located at either side of a breakable portion of the peripheral line respectively; and conductive portions provided at the respective through holes of the insulation layer and electrically connected to the peripheral line through the through holes. With the array substrate having the above configuration, when the peripheral line of the array substrate is broken, a repairing sheet can be spanned the conductive portions at either side of the broken portion, such that portions of the peripheral line on either side of the broken portion are electrically connected through the repairing sheet, thereby the broken portion of the peripheral line can be conveniently repaired so that the array substrate can be used normally.

Abstract: A method of fabricating a BGA carrier, the method comprising combining a conductive portion and a molded dielectric portion, the dielectric portion having a top surface, a bottom surface and an inner surface, the inner surface intersecting said top surface and said bottom surface, the inner surface forming a cavity for receiving a semiconductor die; selectively bonding the semiconductor die to a top surface of the conductive portion; selectively etching part of the conductive portion; and applying solder resist to a bottom surface of the conductive portion.

Abstract: An embodiment is a method including depositing a first flowable film over a substrate in a processing region, the first flowable film comprising silicon and nitrogen, curing the first flowable film in a first step at a first temperature with a first process gas and ultra-violet light, the first process gas including oxygen, curing the first flowable film in a second step at a second temperature with a second process gas and ultra-violet light, the second process gas being different than the first process gas, and annealing the cured first flowable film at a third temperature to convert the cured first flowable film into a silicon oxide film over the substrate.

Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.

Abstract: A method comprising forming on a common support (6) one or more series of multi-layer electronic devices (covering the areas 2a, 2b respectively), and then separating the electronic devices; wherein the devices comprise one or more organic layers (9), and the method comprises depositing one or more of the organic layers (9) as a respective continuous layer extending at least from one end of the one or more series of devices to an opposite end of the one or more series of devices.

Abstract: A method for processing a semiconductor wafer is provided. The method includes performing a discharging process over the semiconductor wafer in a discharging chamber which is enclosed. The method further includes processing the semiconductor wafer by use of a first processing module after the discharging process. During the discharging process, charged particles applied on the semiconductor wafer are tuned based on the characteristics of the surface of the semiconductor wafer.

Abstract: An integration method of fabricating optical sensor device and thin film transistor device includes the follow steps. A substrate is provided, and a gate electrode and a bottom electrode are formed on the substrate. A first insulating layer is formed on the gate electrode and the bottom electrode, and the first insulating layer at least partially exposes the bottom electrode. An optical sensing pattern is formed on the bottom electrode. A patterned transparent semiconductor layer is formed on the first insulating layer, wherein the patterned transparent semiconductor layer includes a first transparent semiconductor pattern covering the gate electrode, and a second transparent semiconductor pattern covering the optical sensing pattern. A source electrode and a drain electrode are formed on the first transparent semiconductor pattern.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.

Abstract: The invention provides a method for forming a surface oxide layer on an amorphous silicon including steps: using a HF acid to clean a surface of the amorphous silicon; using a water to clean the surface of the amorphous silicon being cleaned by the HF acid; drying the surface of the amorphous silicon after being cleaned by the water; using an extreme ultraviolet lithography to form a first oxide layer on the surface of the amorphous silicon after being dried; using an oxidizing solution to clean the surface of the amorphous silicon with the first oxide layer to thereby form a second oxide layer; and drying the surface of the amorphous silicon with the second oxide layer. By using the extreme ultraviolet lithography to form the first oxide layer, the surface of the amorphous silicon is given with strong hydrophilicity and therefore the distribution of water would be uniform.

Abstract: An apparatus for forming a thin film on a substrate in a reaction container by alternately supplying a raw material gas and a reaction gas into the reaction container under a vacuum atmosphere is provided. The apparatus includes: a raw material gas supply unit installed in an end portion of a supply path of the raw material gas; a pressure adjusting valve installed in an vacuum exhaust path; a pressure regulating valve and an opening and closing valve which are respectively installed in a bypass path detouring the pressure adjusting valve; a tank installed in the middle of the supply path of the raw material gas; a flow rate adjusting valve installed in a downstream side of the tank; and a control unit configured to control the opening and closing valve to be opened when the raw material gas stored in the tank is supplied into the reaction container.

Abstract: A method of forming field effect transistors (FETs), and forming integrated circuit (IC) chip including the FETs. Gates are formed on said semiconductor fins to define multi fin field effect transistors (FinFETs). Dielectric sidewalls on fins protect the sidewalls while the surface is damaged intentionally, e.g., with an implant that leaves source/drain junctions undisturbed. After removing the dielectric sidewalls semiconductor material is grown epitaxially on the sidewalls with the damage retarding growth on the surface. The epi-growth bridges between fins in the same FET. After the damage is repaired, chip processing continues normally.