Abstract: An organic light-emitting display device includes: a substrate; a pixel electrode on the substrate; a pixel defining layer having a first opening exposing a center portion of the pixel electrode; a barrier layer on the pixel defining layer; an intermediate layer including a first common layer, a first emissive layer, and a second common layer sequentially arranged on the pixel electrode, the pixel defining layer, and the barrier layer; and a first opposite electrode covering the intermediate layer. The barrier layer has a second opening that is larger than the first opening and has an undercut structure.

Abstract: A method used in forming a memory array comprises forming a conductive tier atop a substrate, with the conductive tier comprising openings therein. An insulator tier is formed atop the conductive tier and the insulator tier comprises insulator material that extends downwardly into the openings in the conductive tier. A stack comprising vertically-alternating insulative tiers and wordline tiers is formed above the insulator tier. Strings comprising channel material that extend through the insulative tiers and the wordline tiers are formed. The channel material of the strings is directly electrically coupled to conductive material in the conductive tier. Structure independent of method is disclosed.

Abstract: A semiconductor package includes a connection structure having first and second surfaces opposing each other and including a redistribution layer. A semiconductor chip is disposed on the first surface of the connection structure and has connection pads connected to the redistribution layer. An encapsulant is disposed on the first surface of the connection structure and covers the semiconductor chip. A support pattern is disposed on a portion of an upper surface of the encapsulant. A heat dissipation bonding material has a portion embedded in the encapsulant in a region overlapping the semiconductor chip and extends to the upper surface of the encapsulant so as to cover the support pattern. A heat dissipation element is bonded to the upper surface of the encapsulant by the heat dissipation bonding material.

Abstract: A method, comprising retaining a superstrate with a superstrate chuck; applying a pressure to deflect the superstrate toward a substrate, deflection of the superstrate being gradually extended along a radial direction; maintaining a vacuum applied to a perimeter of the superstrate and continuously retaining the superstrate with the chuck while the deflecting the superstrate by the pressure; releasing the vacuum from the perimeter of the superstrate; and releasing the superstrate from the chuck.

Abstract: A method is provided, comprising creating at least one crack at a point on an edge of a stack of at least a substrate and a superstrate; propagating the crack along the periphery; and moving the superstrate relative to the substrate to complete separation of the superstrate from the substrate.

Abstract: An electronic device package includes a first substrate, a second substrate and a conductive layer. The first substrate includes a first bonding pad, and a cavity exposing the first bonding pad. The second substrate is laminated on the first substrate. The second substrate includes a second bonding pad at least partially inserting into the cavity of the first substrate. The conductive layer is disposed in the cavity and at least between the first bonding pad and the second bonding pad to connect the first bonding pad and the second bonding pad.

Abstract: A display panel is provided. The display panel includes at least two first pixels, at least two second pixels, and at least two third pixels. An area of the first pixel, an area of the second pixel, and an area of the third pixel are inversely proportional to a luminous efficiency of a luminescent material of the first pixel, a luminous efficiency of a luminescent material of the second pixel, and a luminous efficiency of a luminescent material of the third pixel, respectively. The disclosure can avoid the drawback of color shift of the display panel.

Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers f using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N@C—)—(R)—(—C?N); Rx[-C?N(Rz)]y; and R(3-a)-N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: An integrated circuit having logic and static random-access memory (SRAM) devices includes at least three active regions with gate terminals. Dielectric pillars are disposed between the active regions of the integrated circuit. A pillar is disposed symmetrically between two active regions of the logic device. A pillar is disposed asymmetrically between a p-channel field effect transistor (pFET), and an n-channel field effect transistor (nFET) of the SRAM device.

Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include placing conductive wires in a wire guide, where conductive wires are placed over a first semiconductor substrate having first doped regions and second doped regions. The method can include aligning the conductive wires over the first and second doped regions, where the wire guide aligns the conductive wires substantially parallel to the first and second doped regions. The method can include bonding the conductive wires to the first and second doped regions. The bonding can include applying a mechanical force to the semiconductor substrate via a roller or bonding head of the wire guide, where the wire guide inhibits lateral movement of the conductive wires during the bonding.

Abstract: Systems and methods for releasing semiconductor dies during pick and place operations are disclosed. In one embodiment, a system for handling semiconductor dies comprises a support member positioned to carry at least one semiconductor die releasably attached to a support substrate. The system further includes a picking device having a pick head coupleable to a vacuum source and positioned to releasably attach to the semiconductor die at a pick station. The system still further includes a cooling member coupleable to a cold fluid source and configured to direct a cold fluid supplied by the cold fluid source toward the support substrate at the pick station. The cold fluid cools a die attach region of the substrate where the semiconductor die is attached to the substrate to facilitate removal of the semiconductor die.

Abstract: A magnetic sensor whose output characteristic is less sensitive to the environmental temperature is provided. Magnetic sensor 1 has free layer 24 whose magnetization direction changes in response to an external magnetic field, pinned layer 22 whose magnetization direction is fixed with respect to the external magnetic field, spacer layer 23 that is located between pinned layer 22 and free layer 24 and that exhibits a magnetoresistance effect, and at least one magnet film 25 that is disposed on a lateral side of free layer 24 and that applies a bias magnetic field to free layer 24. A relationship of 0.7 ?TC_HM/TC_FL?1.05 is satisfied, where TC_HM is Curie temperature of the magnet film, and TC_FL is Curie temperature of the free layer.

Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically

Abstract: Provided is an SiC substrate evaluation that includes irradiating a first surface of an SiC substrate which is cut out from an SiC ingot with excitation light before an epitaxial film is laminated on the first surface to perform photoluminescence measurement.

Abstract: The present disclosure relates to a packaging process to enhance performance of a wafer-level package. The disclosed package includes multiple mold compounds, a multilayer redistribution structure, and a thinned die with a device layer and die bumps underneath the device layer. The multilayer redistribution structure includes package contacts at a bottom of the multilayer redistribution structure and redistribution interconnects connecting the die bumps to the package contacts. A first mold compound resides around the thinned die to encapsulate sidewalls of the thinned die, and extends beyond a top surface of the thinned die to define an opening over the thinned die. A second mold compound resides between the multilayer redistribution structure and the first mold compound to encapsulate a bottom surface of the device layer and each die bump. A third mold compound fills the opening and is in contact with the top surface of the thinned die.

Abstract: A method for bonding at least three substrates to form a substrate stack, wherein the substrate stack has at least one lowermost substrate a middle substrate, and an upper substrate. The method includes the following steps: aligning the middle substrate to the lowermost substrate and bonding the middle substrate to the lowermost substrate, then aligning the upper substrate and bonding the upper substrate to the middle substrate, wherein the upper substrate is aligned to the lowermost substrate.

Abstract: The present disclosure relates to a wafer-level fan-out package that includes a first thinned die, a second die, a multilayer redistribution structure underneath the first thinned die and the second die, a first mold compound over the second die, a second mold compound over the multilayer redistribution structure, and around the first thinned die and the second die, and a third mold compound. The second mold compound extends beyond the first thinned die to define an opening within the second mold compound and over the first thinned die, such that a top surface of the first thinned die is at a bottom of the opening. A top surface of the first mold compound and a top surface of the second mold compound are coplanar. The third mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: The semiconductor device includes a first semiconductor substrate, a first wiring layer, a second wiring layer, a second semiconductor substrate, a first conductive portion, and a second conductive portion. The first wiring layer includes a first electrode pad and a first inductor electrically connected with each other. The second wiring layer includes a second inductor and a second electrode pad electrically connected with each other. The first conductive portion is formed in the second semiconductor substrate, the second wiring layer, and the first wiring layer so as to reach the first electrode pad from the back surface of the second semiconductor substrate. The second conductive portion is formed in the second semiconductor substrate and the second wiring layer so as to reach the second electrode pad from the back surface of the second semiconductor substrate. The first inductor and the second inductor are disposed so as to face each other.

Abstract: A SiC substrate (1) has an off angle ?°. A SiC epitaxial layer (2) having a film thickness of Tm ?m is provided on the SiC substrate (1). Triangular defects (3) are formed on a surface of the SiC epitaxial layer (2). A density of triangular defects (3) having a length of Tm/Tan ?×0.9 or more in a substrate off direction is denoted by A. A density of triangular (3) defects having a length smaller than Tm/Tan ?×0.9 in the substrate off direction is denoted by B. B/A?0.5 is satisfied.

Abstract: Methods and apparatus for processing a substrate are provided. The apparatus, for example, can include a process chamber comprising a chamber body defining a processing volume and having a view port coupled to the chamber body; a substrate support disposed within the processing volume and having a support surface to support a substrate; and an infrared temperature sensor (IRTS) disposed outside the chamber body adjacent the view port to measure a temperature of the substrate when being processed in the processing volume, the IRTS movable relative to the view port for scanning the substrate through the view port.