Abstract: A foldable display device includes a display panel. The display panel includes a bending portion. A support structure supports the bending portion. The support structure includes a tube.

Abstract: A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.

Abstract: An LED wafer processing method includes a dividing step of rotatably mounting a first cutting blade having a first width in a first cutting unit, holding an LED wafer on a holding table, and then relatively moving the first cutting unit and the holding table to cut the wafer along each division line formed on the wafer, thereby forming a full-cut groove along each division line to thereby divide the wafer into individual chips. The method further includes rotatably mounting a second cutting blade having a second width larger than the first width in a second cutting unit after performing the dividing step, and then relatively moving the second cutting unit and the holding table to thereby polish the opposed side surfaces of the full-cut groove formed along each division line, whereby a polished groove larger in width than the full-cut groove is formed along each full-cut groove.

Abstract: A standard direction (S) is a horizontal direction (a direction along X direction in the drawing). A base material (200) is supported by a frame body (250) so that a second surface (204) of the base material (200) is oriented obliquely upward from the standard direction (S). Thereby, a reference direction (R) is oriented obliquely upward from the standard direction (S). A light distribution of light from a light-emitting region (242) (more specifically, a light-emitting unit (172)) has a maximum value in a first direction (D1). The first direction (D1) is different from the standard direction (S). Specifically, an angle formed between the first direction (D1) and the reference direction (R) is greater than an angle formed between the standard direction (S) and the reference direction (R).

Abstract: A method for manufacturing a micro light emitting diode device is provided. A connection layer and epitaxial structures are formed on a substrate. A first pad is formed on each of the epitaxial structures. A first adhesive layer is formed on the connection layer, and the first adhesive layer encapsulates the epitaxial structures and the first pads. A first substrate is connected to the first adhesive layer. The substrate is removed, and a second substrate is connected to the connection layer through a second adhesive layer. The first substrate and the first adhesive layer are removed. The connection layer located between any two adjacent epitaxial structures are partially removed to form a plurality of connection portions. Each of the connection portions is connected to the corresponding epitaxial structure, and a side edge of each of the connection portions protrudes from a side wall surface of the corresponding epitaxial structure.

Abstract: Implementations described herein generally relate to methods for forming a low-k dielectric material on a semiconductor substrate. More specifically, implementations described herein relate to methods of forming a silicon oxide film at high pressure and low temperatures. In one implementation, a method of forming a silicon oxide film is provided. The method comprises loading a substrate having a silicon-containing film formed thereon into a processing region of a high-pressure vessel. The method further comprises forming a silicon oxide film on the silicon-containing film. Forming the silicon oxide film on the silicon-containing film comprises exposing the silicon-containing film to a processing gas comprising steam at a pressure greater than about 1 bar and maintaining the high-pressure vessel at a temperature between about 100 degrees Celsius and about 500 degrees Celsius.

Abstract: A semiconductor device capable of lowering a temperature coefficient and increasing a sheet resistance value (?s value) and a manufacturing method thereof are provided. The resistive layer RL is made of polycrystalline silicon containing boron. The concentration distribution of boron in the thickness direction of the resistive layer RL includes a concentration peak PC and a low concentration portion LC having a concentration of boron lower than the concentration of boron in the concentration peak PC by two orders of magnitude or more.

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

Abstract: A flexible organic light emitting display device includes a flexible substrate, an insulating layer, a polymer flat layer, an anode, and a pixel isolation layer. The pixel isolation layer and the anode are alternately disposed on the polymer flat layer, and the pixel isolation layer includes a first pixel isolation layer disposed on a bent area and a second pixel isolation layer disposed on a flat area. A thickness of the first pixel isolation layer is greater than a thickness of the second pixel isolation layer. A method of manufacturing an organic light emitting display device is further provided by increasing the thickness of the pixel isolation layer of the bent area, mechanical stress generated by a flexible organic light emitting diode (OLED) display device during bending can be reduced, thereby improving the bending performance of the flexible OLED display device.

Abstract: An embodiment provides a semiconductor element, which comprises: a plurality of semiconductor structures, each of which comprises a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and a first recess extending through the second conductive semiconductor layer and the active layer to a partial area of the first conductive semiconductor layer; a second recess disposed between the plurality of semiconductor structures; a first electrode disposed at the first recess and electrically connected to the first conductive semiconductor layer; a reflective layer disposed under the second conductive semiconductor layer; and a protrusion part disposed on the second recess and protruding higher than the upper surfaces of the semiconductor structures, wherein a surface, on which the first electrode contacts the first conductive semiconductor layer in the first recess, is 300

Abstract: The present disclosure provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following operations. An intermediate layer is formed in the semiconductor device. A voltage is applied to the intermediate layer. A unit cell of the intermediate layer is stretched or compressed by the voltage. The polarity of the intermediate layer is changed by the voltage.

Abstract: A semiconductor device according to an embodiment comprises a substrate and a first semiconductor chip provided above the substrate. A second semiconductor chip is provided above the first semiconductor chip. A spacer chip is provided between the first semiconductor chip and the second semiconductor chip with regard to a direction orthogonal to a mount surface of the substrate, the spacer chip being made of a first resin material. A first adhesive material is provided between the spacer chip and the substrate or the first semiconductor chip. A second adhesive material is provided between the spacer chip and the second semiconductor chip. A second resin material covers the first and second semiconductor chips and the spacer chip.

Abstract: An active three-terminal superconducting device having an intersection region at which a hot spot may be controllably formed is described. The intersection region may exhibit current crowding in response to imbalances in current densities applied to channels connected to intersection region. The current crowding may form a hot spot, in which the superconducting device may exhibit a measurable resistance. In some cases, a three-terminal superconducting device may be configured to sense an amount of superconducting current flowing in a channel or loop without having to perturb the superconducting state or amount of current flowing in the channel. A three-terminal superconducting device may be used to read out a number of fluxons stored in a superconducting memory element.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A circuit module (301) includes a first substrate (201), a first module (101), a sealing resin portion (3), and a conductive material film (7). The first substrate (201) has a first principal surface (201a). The first module (101) is mounted on the first principal surface (201a). The sealing resin portion (3) is formed on the first principal surface (201a) and covers the first module (101). The conductive material film (7) covers a side of the sealing resin portion (3). The first module (101) includes a conductive material portion and a device which may produce heat and which is mounted on the conductive material portion. The conductive material portion connects with the conductive material film (7) on the side of the sealing resin portion (3).

Abstract: Processes form integrated circuit apparatuses that include parallel fins, wherein the fins are patterned in a first direction. Parallel gate structures intersect the fins in a second direction perpendicular to the first direction, wherein the gate structures have a lower portion adjacent to the fins and an upper portion distal to the fins. Source/drain structures are positioned on the fins between the gate structures. Source/drain contacts are positioned on the source/drain structures and multiple insulator layers are positioned between the gate structures and the source/drain contacts. Additional upper sidewall spacers are positioned between the upper portion of the gate structures and the multiple insulator layers.

Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a RDL structure and a protection layer. The die includes a first surface and a second surface opposite to each other. The encapsulant is aside the die. The RDL structure is electrically connected to the die though a plurality of conductive bumps. The RDL structure is underlying the second surface of the die and the encapsulant. The protection layer is located over the first surface of the die and the encapsulant. The protection layer is used for controlling the warpage of the package structure.

Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.