Abstract: A thermal electrical (TE) interface comprises a primary fiber thermal interface (FTI) having a first side configured to contact a heatsink, and a second side. The primary fiber thermal interface has a thickness ranging from 0.3 mm to 4 mm. A secondary fiber thermal interface (FTI) has a first side configured to contact the second side of the primary FTI, a second side configured to contact circuit components to dissipate heat from the circuit components through the first side of the primary FTI. The secondary fiber thermal interface has a thickness equal to or greater than the primary FTI.

Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include forming a first cut portion from a conductive foil. The method can also include aligning the first cut portion to a first doped region of a first semiconductor substrate. The method can include bonding the first cut portion to the first doped region of the first semiconductor substrate. The method can also include aligning and bonding a plurality of cut portions of the conductive foil to a plurality of semiconductor substrates.

Abstract: Disclosed are a flat display panel that is capable of preventing a different appearance between a camera index light source (CIL) and an ambient light sensor hole and a method of manufacturing the same. The flat display panel is configured such that, on a first substrate, partitioned into a pixel region of a display area and a CIL hole part and an ambient light sensor hole part of a non-display area, a gate insulating layer, a first passivation film, a planarization film, and a second passivation film are not present at the CIL hole part or at the ambient light sensor hole part or such that only the planarization film is present at the CIL hole part and the ambient light sensor hole part.

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

Abstract: Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform specified application performance parameters. In embodiments, CEM devices fabricated at a first stage of a wafer fabrication process, such as a front-end-of-line stage, may differ from CEM devices fabricated at a second stage of a wafer fabrication process, such as a middle-of-line stage or a back-end-of-line stage, for example.

Abstract: There is described a photodetector for detecting incoming infrared light. The photodetector generally has a substrate; an i-type semiconductor region extending along the substrate, the i-type semiconductor region being sandwiched between a p-type semiconductor region and an n-type semiconductor region; a grating coupler being optically connected to one of two ends of the i-type semiconductor region, the grating coupler redirecting incoming infrared light into and along the i-type semiconductor region via the one of the two ends of the i-type semiconductor region for propagation of infrared light along the i-type semiconductor region; and a photocurrent detection circuit electrically connected to the p-type semiconductor region and to the n-type semiconductor region for detecting a photocurrent resulting from said propagation.

Abstract: In a method of manufacturing a vertical semiconductor device, an insulation layer and a sacrificial layer are alternatively and repeatedly formed on a substrate to define a structure. The structure is etched to form a hole therethrough that exposes the substrate. A first semiconductor pattern is formed in a lower portion of the hole, and a blocking pattern, a charge storage pattern, a tunnel insulation pattern and a first channel pattern are formed on a sidewall of the hole. A second channel pattern is formed on the first channel pattern and the semiconductor pattern, and a second semiconductor pattern is formed on a portion of the second channel pattern on the semiconductor pattern to define an upper channel pattern including the second channel pattern and the second semiconductor pattern. The sacrificial layers are replaced with a plurality of gates, respectively, including a conductive material.

Abstract: An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars.

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over an interlayer dielectric layer, and a block mask is formed that covers an area on the hardmask. A sacrificial layer is formed over the block mask and the hardmask, and the sacrificial layer is patterned to form a mandrel that extends across the block mask.

Abstract: A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.

Abstract: A light-emitting semiconductor chip, a light-emitting component and a method for producing a light-emitting component are disclosed. In an embodiment a light-emitting semiconductor chip includes a substrate having a top surface, a bottom surface opposite the top surface and a first side surface extending transversely or perpendicularly to the bottom surface, a semiconductor body arranged on the top surface of the substrate, the semiconductor body comprising an active region configured to generate light and a contacting comprising a first current distribution structure and a second current distribution structure, which is formed to supply current to the active region, wherein the semiconductor chip is free of any connection point on a side of the semiconductor body facing away from the substrate and on the bottom surface of the substrate, and wherein the connection point is a connection point for electrically contacting the first and second current distribution structures.

Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.

Abstract: A semiconductor device and a fabrication method are provided. The fabrication method includes providing a gate structure on a substrate and a first protective layers on the gate structure; forming an initial sidewall spacer on a sidewall of each of the gate structure and the first protective layer; forming a first sidewall spacer on a sidewall of the initial sidewall spacer, the first and initial sidewall spacers being made of different materials; forming a second sidewall spacer by removing a portion of the initial sidewall spacer, leaving a trench formed above the second sidewall spacer and between the first sidewall spacer and the first protective layer; and forming a second protective layer in the trench, the second protective layer and the first sidewall spacer being made of a same material. The second sidewall spacer has a top surface higher than or level with a top surface of the gate structure.

Abstract: A method of forming a semiconductor structure comprises forming a plurality of fins disposed over a top surface of a substrate and forming one or more vertical transport field-effect transistors (VTFETs) from the plurality of fins using a replacement metal gate (RMG) process. A gate surrounding at least one fin of a given one of the VTFETs comprises a gate self-aligned contact (SAC) capping layer disposed over a gate contact metal layer, the gate contact metal layer being disposed adjacent an end of the at least one fin.

Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically

Abstract: An object is to provide a technology capable of suppressing a crack of a crystalline nitride layer which is generated due to a stress caused by difference in thermal expansion coefficients between a crystalline nitride and diamond. A semiconductor device includes a crystalline nitride layer, a structure containing silicon, and a diamond layer. The structure is disposed on a first main surface of the crystalline nitride layer. The diamond layer is disposed at least on a lateral portion of the structure and has a void between the diamond layer and the first main surface of the crystalline nitride layer. The void is a stress absorbing space, for example.

Abstract: Methods of fabricating a solar cell, and system for electrically coupling solar cells, are described. In an example, the methods for fabricating a solar cell can include placing conductive wires in a wire guide, where conductive wires are placed over a first semiconductor substrate having first doped regions and second doped regions. The method can include aligning the conductive wires over the first and second doped regions, where the wire guide aligns the conductive wires substantially parallel to the first and second doped regions. The method can include bonding the conductive wires to the first and second doped regions. The bonding can include applying a mechanical force to the semiconductor substrate via a roller or bonding head of the wire guide, where the wire guide inhibits lateral movement of the conductive wires during the bonding.

Abstract: The present disclosure provides a method that includes coating an edge portion of a wafer by a first chemical solution including a chemical mixture of an acid-labile group, a solubility control unit and a thermal acid generator; curing the first chemical solution to form a first protecting layer on the edge portion of the wafer; coating a resist layer on a front surface of the wafer; removing the first protecting layer by a first removing solution; and performing an exposing process to the resist layer.

Abstract: A method of manufacturing three-dimensional semiconductor device, comprising the steps of: a) forming a device unit on a substrate, the said device includes a plurality of stack structures composed of the first material layer and the second material layer stacked along a direction perpendicular to the substrate surface; b) forming a contact lead-out region around the said device unit, the contact lead-out region comprises a plurality of sub-partitions, each of the sub-partitions respectively exposes a different second material layer; c) forming a photoresist on said substrate, covering said plurality of sub-partitions, exposing a portion of said second material layer; d) using the photoresist as a mask, simultaneously etching the portion of the second material layer exposed by said plurality of sub-partitions, until another second material layer beneath said second material layer is exposed; e) slimming the size of the photoresist to expose a portion of said another second material layer; f) repeating said st

Abstract: A semiconductor device includes a base plate, a plurality of semiconductor units provided in parallel on the base plate, the plurality of semiconductor units implementing a pair, each semiconductor unit including a semiconductor chip and a rod-shaped unit-side control terminal, the unit-side control terminal being connected to the semiconductor chip, the unit-side control terminal extending opposite to the base plate; and an interface unit including a box-shaped accommodating portion, the accommodating portion being provided on the plurality of semiconductor units, the accommodating portion including an internal wiring and a rod-shaped external-connecting control terminal, the internal wiring being connected to each of the plurality of the unit-side control terminals extending from the plurality of semiconductor units, the external-connecting control terminal extending to the outside opposite to the semiconductor units, the external-connecting control terminal being connected to the internal wiring.