Abstract: Methods and apparatuses for selectively depositing silicon oxide on a silicon oxide surface relative to a silicon nitride surface are described herein. Methods involve pre-treating a substrate surface using ammonia and/or nitrogen plasma and selectively depositing silicon oxide on a silicon oxide surface using alternating pulses of an aminosilane silicon precursor and an oxidizing agent in a thermal atomic layer deposition reaction without depositing silicon oxide on an exposed silicon nitride surface.

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

Abstract: A method for forming a hexagonal boron nitride (h-BN) thin film is provided. According to the method, an alumina thin film including amorphous alumina or gamma-alumina is prepared. An h-BN thin film is synthesized at equal to or less than 750° C. on the alumina thin film. A mono-layer thickness of the h-BN film is equal to or less than 0.40 nm.

Abstract: A semiconductor device includes a substrate having a fin structure extending along a first direction. The fin structure protrudes from a top surface of a trench isolation region and has a first height. A plurality of gate lines including a first gate line and a second gate line extend along a second direction and striding across the fin structure. The first gate line has a discontinuity directly above a gate cut region. The second gate line is disposed in proximity to a dummy fin region, and does not overlap with the dummy fin region. The fin structure has a second height within the dummy fin region, and the second height is smaller than the first height.

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.

Abstract: A dual-gate, self-aligned lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure, a lateral gate including a first dielectric layer and a first conductive layer stacked on the silicon semiconductor structure in a thickness direction, and a vertical gate. The vertical gate includes a second dielectric layer and a second conductive layer disposed in a trench of the silicon semiconductor structure, the second dielectric layer defining an edge of the lateral gate in a lateral direction. A method for forming a dual-gate, self-aligned LDMOS transistor includes (a) forming a vertical gate of the LDMOS transistor in a trench of a silicon semiconductor structure and (b) defining a lateral edge of a lateral gate of the LDMOS transistor using the vertical gate.

Abstract: A method of forming a nitrogen-incorporated silicon or metal oxide film, includes (i) depositing by a plasma a silicon or metal oxide film on a substrate using a precursor containing a silicon or metal and an oxidizing gas, said plasma having a first plasma density; and (ii) nitriding by a plasma the silicon or metal oxide film using a nitriding gas without using any precursor, said plasma having a second plasma density which is higher than the first plasma density.

Abstract: A manufacturing method of an array substrate, an array substrate and a display apparatus are provided. The manufacturing method includes: providing a base substrate; sequentially forming an active layer and a first insulating layer that covers the active layer on the base substrate; performing one patterning process on the first insulating layer, so as to form a first through hole and a second through hole that expose the active layer in the first insulating layer, and form a first recess at a surface of the first insulating layer; forming a conductive layer on the patterned first insulating layer, with the conductive layer being filled in the first through hole, the second through hole and the first recess; conducting a grinding process to form a source electrode, a drain electrode and a pixel electrode are formed respectively.

Abstract: A semiconductor device includes a first circuit formed on a substrate in a first region, a second circuit formed on the substrate in a second region and including one or more transistors, and connections between the first circuit and respective gates of the transistors of the second circuit. The substrate includes a first semiconductor material and the second circuit includes one or more transistors having channels formed from a second semiconductor material different from the first semiconductor material.

Abstract: A GaN on diamond wafer and method for manufacturing the same is provided. The method comprising: disposing a GaN device or wafer on a substrate, having a nucleation layer disposed between the substrate and a GaN layer; affixing the device to a handling wafer; removing the substrate and substantially all the nucleation layer; and bonding the GaN layer to a diamond substrate.

Abstract: Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.

Abstract: A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

Abstract: A method of processing an engineered substrate structure includes providing an engineered substrate structure including a polycrystalline substrate and an engineered layer encapsulating the polycrystalline substrate, forming a sacrificial layer coupled to the engineered layer, joining a solid state device structure to the sacrificial layer, forming one or more channels in the solid state device structure by removing one or more portions of the solid state device structure to expose one or more portions of the sacrificial layer, flowing an etching chemical through the one or more channels to the one or more exposed portions of the sacrificial layer, and dissolving the sacrificial layer by interaction between the etching chemical and the sacrificial layer, thereby separating the engineered substrate structure from the solid state device structure.

Abstract: The film forming apparatus includes a reaction chamber in which a substrate subjected to film forming processing can be placed, a gas supplier provided in an upper part of the reaction chamber, having a portion where gas is introduced and gas supply holes to face the substrate, a source-gas introducing line introducing a source gas into the gas supplier, a replacement-gas introducing line introducing a replacement gas into the gas supplier, a discharge line discharging the replacement gas along with a remaining source gas which is the source gas remaining in the gas supplier from the gas supplier; and a controller controlling one of an introduction amount of the replacement gas and a discharge amount of the remaining source gas and the replacement gas to be an amount corresponding to the other amount.

Abstract: A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.

Abstract: A method of processing a target object is provided. In the method, the target object including a first protrusion portion, a second protrusion portion, an etching target layer and a groove portion, the etching target layer having a region belonging to the first protrusion portion and a region belonging to the second protrusion portion, the groove portion being provided on a main surface of the target object, being provided on the etching target layer and being defined by the first protrusion portion and the second protrusion portion, and an inner surface of the groove portion being included in the main surface of the target object is prepared, and a first sequence is repeatedly performed N times (N is an integer equal to or larger than 2). The first sequence includes (a) forming a protection film conformally on the main surface; and (b) etching a bottom portion of the groove portion with plasma of a gas generated after the process a is performed.