Patents Examined by Evan Pert
  • Patent number: 9530877
    Abstract: According to one embodiment, a III-nitride transistor includes a conduction channel formed between first and second III-nitride bodies, the conduction channel including a two-dimensional electron gas. The transistor also includes at least one gate dielectric layer having a charge confined within to cause an interrupted region of the conduction channel and a gate electrode operable to restore the interrupted region of the conduction channel. The transistor can be an enhancement mode transistor. In one embodiment, the gate dielectric layer is a silicon nitride layer. In another embodiment, the at least one gate dielectric layer is a silicon oxide layer. The charge can be ion implanted into the at least one gate dielectric layer. The at least one gate dielectric layer can also be grown with the charge.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: December 27, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9511997
    Abstract: A method for forming an integrated circuit device includes forming a dielectric layer onto a first substrate, forming a sacrificial material into a sacrificial cavity formed into the dielectric layer, forming a membrane layer over the dielectric layer and sacrificial material, releasing the sacrificial material through at least one via formed through the membrane layer, and bonding a capping substrate to the membrane layer such that a second cavity is formed, the second cavity being connected to the sacrificial cavity though a via formed into the membrane layer.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: December 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wen Cheng, Chia-Hua Chu
  • Patent number: 9515212
    Abstract: A method for manufacturing a solar cell includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: December 6, 2016
    Assignee: LG ELECTRONICS INC.
    Inventors: Kyoungsoo Lee, Seongeun Lee
  • Patent number: 9508485
    Abstract: A signal isolator apparatus includes a first substrate for supporting input circuitry including a high frequency oscillator circuit for receiving an input signal, a second substrate for supporting output circuitry including a detector circuit for providing an output signal; and a third substrate having parallel conductive layers separated by insulation. The third substrate has an upper conductive shield formed in a second conductive layer and a lower conductive shield formed in a fifth conductive layer. A transformer is formed between the upper and lower conductive shields and includes a primary winding formed in a third conductive layer and a secondary winding formed in a fourth conductive layer. The oscillator circuit is connected to the primary winding and adapted to excite the primary winding at a first frequency in response to the input signal, and the detector circuit is connected to the secondary winding and adapted to selectively sense the first frequency and provide the output signal.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: November 29, 2016
    Assignee: VLT, Inc.
    Inventor: Patrizio Vinciarelli
  • Patent number: 9508874
    Abstract: A photovoltaic module including a dielectric tunneling layer and methods of forming a photovoltaic module with a dielectric tunneling layer.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 29, 2016
    Assignee: FIRST SOLAR, INC.
    Inventors: Benyamin Buller, Chungho Lee, Rui Shao, Gang Xiong, Zhibo Zhao
  • Patent number: 9508700
    Abstract: The present invention relates to a semiconductor device used in power equipment. The semiconductor device includes: a base plate; an insulating substrate mounted on the base plate; a power switching element bonded to the insulating substrate with a solder layer; and the base plate, the insulating substrate, and the power switching element forming a module, a control substrate located above the module. The control substrate includes a variable gate voltage circuit measuring a collector-emitter voltage of the power switching element and changing a gate voltage such that the power switching element is supplied with given target power determined by a product of the collector-emitter voltage and a collector current.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hideo Komo, Takeshi Omaru, Shoji Saito
  • Patent number: 9502405
    Abstract: A plurality of contact trenches are formed in a semiconductor structure. The plurality of contact trenches are formed with a contact opening width selected to result in improper contact trench formation in a random number of the plurality of contact trenches. Devices are formed from the semiconductor structure using the plurality of contact trenches, wherein devices formed with improperly formed contact trenches are defective and devices formed with properly formed contact trenches are not defective. One or more measurements are performed to determine which devices are defective and which devices are not defective. The results of the measuring step represent a unique authentication code for an integrated circuit in which the devices are formed. Advantageously, the unique authentication code represents a physically unclonable function.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: November 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 9498852
    Abstract: Laser hybrid welding systems adapted to identify and/or fix a weld defect occurring during a laser hybrid welding process are provided. Embodiments of the laser hybrid welding system may include one or more devices that provide feedback to a controller regarding one or more weld parameters. One embodiment of the laser hybrid welding system includes sensors that are adapted to measure the weld voltage and/or amperage during the welding process and transmit the acquired data to the controller for processing. Another embodiment of the laser hybrid welding system includes a lead camera and a lag camera that film an area directly in front of the weld location and directly behind the weld location.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: November 22, 2016
    Assignee: ILLINOIS TOOL WORKS INC.
    Inventor: Bruce Patrick Albrecht
  • Patent number: 9502379
    Abstract: A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.
    Type: Grant
    Filed: July 7, 2015
    Date of Patent: November 22, 2016
    Assignee: SCHOTTKY LSI, INC.
    Inventor: Augustine Wei-Chun Chang
  • Patent number: 9496502
    Abstract: The present invention relates inter alia to novel compositions, compounds and formulations of multi-charged organic cations or anions having a functional organic group or a non-functional organic group. The present invention further relates to devices comprising the these compositions, compounds or formulations.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: November 15, 2016
    Assignee: Merck Patent GmbH
    Inventors: Junyou Pan, Amir Hossain Parham
  • Patent number: 9496410
    Abstract: A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 9496175
    Abstract: A semiconductor device includes a substrate that has a cell and a peripheral area, and an insulating layer. The insulating layer includes a first region located on the cell area and having outer edge along the cell area, a second region located on the peripheral area and having inner edge along the cell area, a third region located on an area between the cell and the peripheral area and a fourth region located between the second and the third region and forming a boundary with the third region. A conductive member is embedded in the first and the third region and no conductive member is embedded in the fourth region. The boundary has a curved portion.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: November 15, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keisuke Ito
  • Patent number: 9472402
    Abstract: Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 18, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Deok-kee Kim, Kenneth T. Settlemyer, Jr., Kangguo Cheng, Ramachandra Divakaruni, Carl J. Radens, Dirk Pfeiffer, Timothy J. Dalton, Katherina E. Babich, Arpan P. Mohorowala, Harald Okorn-Schmidt
  • Patent number: 9463976
    Abstract: A method and apparatus are described for fabricating a high aspect ratio MEMS sensor device having multiple vertically-stacked inertial transducer elements (101B, 110D) formed in different layers of a multi-layer semiconductor structure (100) and one or more cap devices (200, 300) bonded to the multi-layer semiconductor structure (100) to protect any exposed inertial transducer element from ambient environmental conditions.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 11, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Robert F. Steimle, Paul M. Winebarger
  • Patent number: 9458550
    Abstract: Systems and methods for separating components of a multilayer stack of electronic components are disclosed herein. The multilayer stack may include an electronic assembly, a substrate, and a sacrificial anode portion that is located between the electronic assembly and the substrate and that operatively attaches the electronic assembly to the substrate. The methods may include locating the multilayer stack within an electrically conductive fluid to form an electrochemical cell and generating a potential difference between a cathode portion of the electronic assembly and the sacrificial anode portion. The methods further may include separating the electronic assembly from the substrate by electrochemically oxidizing the sacrificial anode portion to dissolve the sacrificial anode portion within the electrically conductive solution.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: October 4, 2016
    Assignee: The Boeing Company
    Inventors: Robyn L. Woo, Xiaobo Zhang, Christopher M. Fetzer, Eric M. Rehder
  • Patent number: 9460921
    Abstract: A nanowire article includes a substrate; a plurality of nanowires disposed on the substrate, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table; and a superlattice layer interposed between the substrate and the plurality of gallium nitride nanowires. A process for producing a nanowire article includes disposing a superlattice layer on a substrate; disposing a first buffer layer on the superlattice layer; contacting the first buffer layer with a precursor; and forming a plurality of nanowires from the precursor on the first buffer layer to form the nanowire article, the nanowires comprising a semiconductor nitride, the semiconductor comprising an element selected from group 3 of the periodic table.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: October 4, 2016
    Assignees: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE, REGENTS OF THE UNIVERISTY OF COLORADO
    Inventors: Kristine A. Bertness, Matthew D. Brubaker, William M. Old
  • Patent number: 9461112
    Abstract: A method of epitaxially growing nitrogen-based compound semiconductor thin films on a semiconductor substrate, which is periodically patterned with grooves. The method can provide an epitaxial growth of a first crystalline phase epitaxial film on the substrate, and block the growth of an initial crystalline phase with barrier materials prepared at the sides of the grooves. Semiconductor devices employing the epitaxial films are also disclosed.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: October 4, 2016
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Patent number: 9449982
    Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: September 20, 2016
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhenyu Lu, Sateesh Koka, James Kai, Raghuveer S. Makala, Yao-Sheng Lee, Jayavel Pachamuthu, Johann Alsmeier, Henry Chien
  • Patent number: 9449677
    Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: September 20, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jiyoung Kim, Yongchul Oh, Dongsoo Woo, Hyun-Woo Chung, Gyoyoung Jin, Sungkwan Choi, Hyeongsun Hong, Yoosang Hwang
  • Patent number: 9441792
    Abstract: Transfer chamber gas purge apparatus are disclosed. The transfer chamber gas purge apparatus has a transfer chamber adapted to contain at least a portion of a transfer robot, the transfer chamber including side walls, a chamber lid, and a chamber floor, wherein the chamber lid has a plurality of distributed chamber inlets. The plurality of distributed chamber inlets may include diffusing elements. Laminar purge gas flow may be provided above the substrate. Systems and methods including a plurality of distributed chamber inlets are disclosed, as are numerous other aspects.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 13, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Edward Ng, Eric A. Englhardt, Travis Morey, Ayan Majumdar, Steve S. Hongkham