Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

Abstract: Disclosed herein is a light fixture. The light fixture includes at least one first light source that emits at a peak wavelength in a range of approximately 380 nm to approximately 420 nm and at least one second light source that emits at a different peak wavelength, wherein a combined light output of the at least one first light source and the at least one second light source emits a colored light that is perceived as white light. The white light is defined by having a color rendering index (CRI) value of more than approximately 50. The at least one second light source that emits at a different peak wavelength consists of an xy coordinate on a International Commission on Illumination (CIE) 1931 xy color space diagram above a black body curve within a bounded area defined by a first line of approximately y=2.23989x?0.382773 and a second line of approximately y=1.1551x?0.195082.

Abstract: After oxidizing a sacrificial semiconductor layer composed of silicon germanium that is located over an insulator layer to form a germanium-enriched region located within a first end of the sacrificial semiconductor layer and having a greater germanium concentration than a remaining portion of the sacrificial semiconductor layer, the remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the germanium-enriched region that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

Abstract: Optoelectronic devices, such as light-emitting diodes, laser diodes, image sensors, optical detectors, etc., made by depositing (growing) one or more epitaxial semiconductor layers on a monocrystalline lamellar/layered substrate so that each layer has a wurtzite crystal structure. In some embodiments, the layers are deposited and then one or more lamellas of the starting substrate are removed from the rest of the substrate. In one subset of such embodiments, the removed lamella(s) is/are partially or entirely removed. In other embodiments, one or more lamellas of the starting substrate are removed prior to depositing the one or more wurtzite-crystal-structure-containing layer(s).

Abstract: An ESD transistor and an ESD protection circuit thereof are provided. An ESD transistor includes a collector region disposed on a surface of a substrate, a sink region disposed vertically below the collector region, and a buried layer protruding horizontally further than the sink region under the sink region.

Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract: A surface light source device is provided that has high light extraction efficiency and high mechanical strength and can suppress a change in color tone at different viewing angles. To that end, the surface light source device includes: an organic EL element including a luminescent layer; and a light-emitting surface structure layer that is disposed in contact with one of the surfaces of the organic EL element and defines a concave-convex structure on the surface on the device light-emitting surface side. The concave-convex structure includes a plurality of concave portions having oblique surfaces and flat portions disposed around the concave portions. The surface light source device further includes a diffusing member on which the light emitted from the luminescent layer is incident, the diffusing member allowing the incident light to pass therethrough or reflecting the incident light in a diffused manner.

Abstract: An image sensor including a semiconductor layer. A light absorber layer couples with the semiconductor layer at a pixel of the image sensor and absorbs incident light to substantially prevent the incident light from entering the semiconductor layer. The light absorber layer heats a depletion region of the semiconductor layer in response to absorbing the incident light, creating electron/hole pairs. The light absorber layer may include one or more narrow bandgap materials.

Abstract: A three-dimensional wafer level packaged (WLP) integrated circuit that includes a pair of opposing circuit cells fabricated on separate wafers that have been bonded together to provide vertical circuit redundancy. The integrated circuits on each of the separate wafers are performance tested prior to the wafers being bonded together so as to designate good performing circuits as active circuit cells and poor performing circuits as inactive circuit cells. The inactive circuit cell for a particular pair of integrated circuits is metalized with a short circuiting metal layer to make it inoperable. The WLP integrated circuit implements a yield-enhancing circuit redundancy scheme on spatially uncorrelated wafers that avoids wasting valuable wafer x-y planar area, which provides cost savings as a result of more wafer area being available for distinct circuits on each wafer rather than sacrificed for traditional side-by-side redundant copies of circuits.

Abstract: Disclosed is an optical detector. The optical detector includes: a first dielectric layer; a graphene optical transmission line formed on the first dielectric layer; a graphene optical detector formed on the first dielectric layer and configured to detect light transmitted along the graphene optical transmission line; electric wires formed on the graphene optical detector; metal pads positioned at both ends of the graphene optical detector and connected with the electric wires; and a second dielectric layer formed on the graphene optical transmission line, in which the graphene optical detector detects an intensity of light incident in a horizontal direction with respect to a surface of the graphene optical transmission line.

Abstract: The present disclosure relates to a device and method for strain inducing or high mobility channel replacement in a semiconductor device. The semiconductor device is configured to control current from a source to a drain through a channel region by use of a gate. A strain inducing or high mobility layer produced in the channel region between the source and drain can result in better device performance compared to Si, faster devices, faster data transmission, and is fully compatible with the current semiconductor manufacturing infrastructure.

Abstract: Disclosed is an LED luminous structure for backlight source with good light emitting efficiency and color light rendering and capable of preventing oxidation or affects overall light quality. The LED luminous structure includes a base, a blue LED chip, a green LED chip, a red phosphor and an encapsulation. The blue and green LED chips are installed on the base, and the red phosphor absorbs is excited by a light emitted from the blue LED chip to produce a red light. The encapsulation is for packaging the aforementioned components. The red phosphor has a particle size of 20-30 ?m, and the encapsulation has a moisture permeability of 10-20 g/m2.24h and an oxygen permeability smaller than 1000 cm3/m2.24h.atm to lower the chance of oxidizing the red phosphor and improve the stability, brightness and color gamut of the LED luminous structure by limiting the range of the particle size.

Abstract: A MEMS device and a method of making a MEMS device are disclosed. In one embodiment a semiconductor device comprises a substrate, a moveable electrode and a counter electrode, wherein the moveable electrode and the counter electrode are mechanically connected to the substrate. The movable electrode is configured to stiffen an inner region of the movable membrane.

Abstract: Methods and apparatus for polysilicon MOS capacitors in a replacement gate process. A method includes disposing a gate dielectric layer over a semiconductor substrate; disposing a polysilicon gate layer over the dielectric layer; patterning the gate dielectric layer and the polysilicon gate layer to form a plurality of polysilicon gates spaced by at least a minimum polysilicon to polysilicon pitch; defining a polysilicon resistor region containing at least one of the polysilicon gates and not containing at least one other of the polysilicon gates, which form dummy gates; depositing a mask layer over an inter-level dielectric layer; patterning the mask layer to expose the dummy gates; removing the dummy gates and the gate dielectric layer underneath the dummy gates to leave trenches in the inter-level dielectric layer; and forming high-k metal gate devices in the trenches in the inter-level dielectric layer. An apparatus produced by the method is disclosed.

Abstract: A semiconductor device, including: a first layer including first transistors, the first transistors are interconnected by at least one metal layer including copper or aluminum; a second layer including second transistors, the first layer is overlaid by the second layer, where the second layer includes a plurality of through layer vias having a diameter of less than 200 nm, where the second transistors include a source contact, the source contact including a silicide, and where the silicide has a sheet resistance of less than 15 ohm/sq.

Abstract: A semiconductor structure includes a substrate and a fin. The fin extends from the substrate and is formed with a hole therethrough. The hole is defined by a confronting pair of wall parts. One of the wall parts is more arcuate than the other of the wall parts. A method for fabricating the semiconductor structure is also disclosed.

Abstract: In one embodiment, the semiconductor die includes a selective epitaxial layer including device regions, and a masking structure disposed around sidewalls of the epitaxial layer. The masking structure is part of an exposed surface of the semiconductor die.

Abstract: According to one embodiment, a light-emitting element comprises: a first electrically-conductive semiconductor layer, a second electrically-conductive semiconductor layer; and an active layer which is disposed between the first electrically-conductive layer and the second electrically-conductive layer, and in which a well layer and a barrier layer are alternately laminated at least once. The active layer comprises: a first region which is disposed between a neighboring barrier layer and well layer, and linearly reduces the energy band gap; and a second region which is disposed between a neighboring well layer and barrier layer, and linearly increases the energy band gap. In the well layer, at least one first region and second region neighboring the same well layer have mutually different thicknesses.

Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.

Abstract: A method and apparatus provide for a roughened back surface of a semiconductor absorber layer of a photovoltaic device to improve adhesion. The roughened back surface may be achieved through an etching process.