Abstract: Embodiments of the present invention disclose a display panel and an encapsulation method thereof, and relate to the field of display technology. The display panel comprises a first substrate and a second substrate which are disposed in opposition to each other. The first substrate and the second substrate are encapsulated by a sealant. In a non-display area of the display panel, a first adsorption layer is disposed on one of the first substrate and the second substrate, and a second adsorption layer is disposed on the other of the first substrate and the second substrate. The first adsorption layer and the second adsorption layer may be attracted to each other by magnetic force. Embodiments of the present invention can effectively avoid the separation of the first substrate and the second substrate due to the stress released during the process of melting the sealant, thereby improving the problem of poor encapsulation caused thereby.

Abstract: Provided is an ink composition including the following components (A), (B), and (C). The component (A) is an anthracene derivative represented by the following formula (A1). The component (B) is an aromatic amine derivative represented by the following formula (B1). The component (C) is a solvent represented by the following formula (C1) and having a boiling point of 110° C. or higher and a solubility of 1 wt % or less in water. where one or more of Ar1 to Ar4 are a heterocyclic group represented by a formula (B1?).

Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures for controlling a threshold voltage on a nanosheet-based transistor. A nanosheet stack is formed over a substrate. The nanosheet stack includes a first nanosheet vertically stacked over a second nanosheet. A tri-layer gate metal stack is formed on each nanosheet. The tri-layer gate metal stack includes an inner nitride layer formed on a surface of each nanosheet, a doped transition metal layer formed on each inner nitride layer, and an outer nitride layer formed on each doped transition metal layer.

Abstract: A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a first region and a second region is provided, a shallow trench isolation (STI) is formed in the substrate to separate the first region and the second region, and a patterned hard mask is formed on the first region and part of the STI, in which the patterned hard mask exposes includes an opening to expose part of the STI. Next, a gas is driven-in through the exposed STI to alter an edge of the substrate on the first region.

Abstract: The present disclosure provides a light emitting element, wherein each of first and second semiconductor layers has first and second pits disposed therein, wherein the first pit has a first depth and the second pit has a second depth smaller than the first depth, and the first and second pits are coupled to each other, wherein a density of the second pits in an upper portion of the second semiconductor layer is lower than a density of the second pits in an upper portion of the first semiconductor layer, wherein a density of the first pits in the upper portion of the second semiconductor layer is equal to a density of the first pits in the upper portion of the first semiconductor layer.

Abstract: A film formation is performed using a target in which a material which is volatilized more easily than gallium when heated at 400° C. to 700° C., such as zinc, is added to gallium oxide by a sputtering method with high mass-productivity which can be applied to a large-area substrate, such as a DC sputtering method or a pulsed DC sputtering method. This film is heated at 400° C. to 700° C., whereby the added material is segregated in the vicinity of a surface of the film. Another portion of the film has a decreased concentration of the added material and a sufficiently high insulating property; therefore, it can be used for a gate insulator of a semiconductor device, or the like.

Abstract: A conductive pattern formation method of the present invention includes a first exposure step of radiating active light in a patterned manner to a photosensitive layer including a photosensitive resin layer provided on a substrate and a conductive film provided on a surface of the photosensitive resin layer on a side opposite to the substrate; a second exposure step of radiating active light, in the presence of oxygen, to some or all of the portions of the photosensitive layer not exposed at least in the first exposure step; and a development step of developing the photosensitive layer to form a conductive pattern following the second exposure step.

Abstract: The present disclosure proposes a metal oxide thin-film transistor, a method of fabricating the metal oxide thin-film transistor, and an array substrate. The metal oxide TFT includes a glass substrate, a gate, a gate insulating layer, a metal oxide active layer, an etching blocking layer with a source hole and a drain hole thereon, a blocking spread layer including a source blocking layer and a drain blocking layer, a source, and a drain. The blocking spread layer is doped with boron ions and/or phosphorus ions of predetermined concentration.

Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.

Abstract: An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a black matrix layer having a plurality of black matrixes on a substrate; forming a switch array layer having a plurality of thin-film transistors on the black matrix layer; forming a color resist layer having a plurality of color resists on the switch array layer; and forming a transparent conductive layer on the color resist layer.

Abstract: The present invention provides a metallic oxide thin film transistor and its manufacturing method, an array substrate and its manufacturing method, as well as a display device, which is belong to the field of thin film transistor manufacturing technology. The method for manufacturing the metallic oxide thin film transistor comprises a step of forming patterns of an oxide active layer and an etch stopping layer through a one-time patterning process.

Abstract: A light emitting assembly is described. In one embodiment, one or more light emitting diode (LED) devices and one or more microcontrollers are bonded to a same side of a substrate, with the one or more microcontrollers to switch and drive the one or more LED devices.

Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.

Abstract: A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity.

Abstract: A vehicle communication system that includes a plurality of functional system modules (FSMs) and a master system module (MSM) coupled to the FSMs. The MSM includes a multi-core processing unit that includes multiple functioning core assemblies (FCAs) and a managing core assembly (MCA). Each FCA includes a substrate carrying a core CPU and an optical interface circuit carried by a first edge of the substrate. The MCA includes a substrate having a first and second major surfaces—the first major surface includes a plurality of rows of electrical connections, each of which are adapted to couple with one of the FCAs to enable communication between the core CPU (of MCA) and the core CPUs (of the FCAs). Each of the FCAs may have a second edge that abuts the first major surface at one of the plurality of rows of electrical connections.

Abstract: According to an embodiment, a MEMS device includes a deflectable membrane including a first plurality of electrostatic comb fingers, a first anchor structure including a second plurality of electrostatic comb fingers interdigitated with a first subset of the first plurality of electrostatic comb fingers, and a second anchor structure including a third plurality of electrostatic comb fingers interdigitated with a second subset of the first plurality of electrostatic comb fingers. The second plurality of electrostatic comb fingers are offset from the first plurality of electrostatic comb fingers in a first direction and the third plurality of electrostatic comb fingers are offset from the first plurality of electrostatic comb fingers in a second direction, where the first direction is different from the second direction.

Abstract: Embodiments of the disclosed technology provide an amorphous oxide thin film transistor (TFT), a method for preparing an amorphous oxide TFT, and a display panel. The amorphous oxide thin film transistor includes: a gate electrode, a gate insulating layer, a semiconductor active layer, a source electrode and a drain electrode. The semiconductor active layer comprises a channel layer and an ohmic contact layer, and the channel layer has a greater content of oxygen than the ohmic contact layer; the channel layer contacts the gate insulating layer, and the ohmic contact layer comprises two separated ohmic contact regions, one of which contacts the source electrode and the other of which contacts the drain electrode.

Abstract: A semiconductor package includes a package substrate having first connecting pads and second connecting pads, and a semiconductor chip mounted on the package substrate. The semiconductor chip includes a semiconductor device comprising a semiconductor substrate and electrically connected to input/output (I/O) pads, and a measuring device formed on the semiconductor device and electrically connected to measuring pads. The I/O pads are electrically connected to the first connecting pads, and the measuring pads are electrically connected to the second connecting pads.

Abstract: A method for manufacturing a solar cell according to an embodiment of the present invention includes preparing a semiconductor substrate having a first conductivity type dopant; ion-implanting a pre-amorphization elements into a front surface of the semiconductor substrate to form an amorphous layer; and forming an emitter layer by ion-implanting second conductivity type dopant into the front surface of the semiconductor substrate. The method then further includes heat-treating the layers to activate the second conductivity type dopant. The method further includes forming a back surface field layer at a back surface of the semiconductor substrate by ion-implanting a first conductivity type dopant.