Patents Examined by F. Niranjan
  • Patent number: 5818748
    Abstract: The high-voltage drivers and decoders of a direct-write EEPROM memory array are separated from the word lines and placed onto separate stacked chips. The separate chips are stacked face-to-face, and force-responsive self-interlocking microconnectors are used to physically and electrically connect the separate chips.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Claude Louis Bertin, John Edward Cronin
  • Patent number: 5781499
    Abstract: The semiconductor memory device of the present invention is provided with at least: a first sync-signal generation circuit that generates and outputs a first sync-signal synchronized with any of a first clock inputted from the outside and a second and third clock inputted after the first clock; a first delay circuit that delays the first sync-signal by a prescribed time interval and outputs the result as a second sync-signal; a first latch circuit that latches the second sync-signal; a second latch circuit that latches the first sync-signal; and a third latch circuit that detects that both the first and second latch circuits have latched the second sync-signal and the first sync-signal, respectively, and latches this detection; the output of the third latch circuit then being used to control a pipeline circuit.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: July 14, 1998
    Assignee: NEC Corporation
    Inventor: Yasuji Koshikawa
  • Patent number: 5774395
    Abstract: A reference cell in a nonvolatile memory is electrically erasable and the electrically erasable character of the memory is exploited to expand the voltage range over which a differential amplifier is useful for sensing the state of a bit. Selected elements of a reference cell are electrically erased and reprogrammed for accurately tuning the sensing of multiple data states in a memory cell. For example, 64 or more data states may be tuned so that a single megabyte of memory is allocated to store six megabytes of information.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: June 30, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert B. Richart, Shyam Garg
  • Patent number: 5748533
    Abstract: A read circuit includes a driver which changes a gate voltage of a memory cell and a sense circuit which identifies when the memory cell trips. The driver searches for the threshold voltage of the memory cell using stages which ramp up gate voltage and stages which ramp down the gate voltage. Each stage ends when the sense circuit senses that the memory cell trips, i.e. begins or stops conducting. Initial stages of the search have high ramp rates so that the gate voltage reaches the threshold voltage. These initial stages can give inaccurate threshold voltage readings because high ramp rates change the gate voltage during the period between the transistor tripping and sensing the trip. Later stages ramp the gate voltage slowly to provide an accurate threshold voltage reading. The low ramp rate of the last stage provides accuracy, and the high ramp rate of the initial stages reduces read time. To further reduce read time, the search process can begin at a median voltage for possible threshold voltages.
    Type: Grant
    Filed: March 26, 1996
    Date of Patent: May 5, 1998
    Assignee: inVoice Technology, Inc.
    Inventors: Frank M Dunlap, Hock C. So, Sau C. Wong
  • Patent number: 5745411
    Abstract: A semiconductor memory device that permits the threshold voltage Vth of a cell transistor to be measured easily and inexpensively is provided. A semiconductor memory device 1 is provided, which has a plurality of cell transistors C for storing predetermined data and is operative at a preset operating voltage Vdd, wherein during normal operation, said operating voltage Vdd is applied between a control gate and a source of each of said cell transistor C, and wherein during testing operation, a test voltage Vcc which is at lower potential than the operating voltage Vdd is applied between the control gate and source of each of said cell transistors C independently of the operating voltage Vdd.
    Type: Grant
    Filed: December 7, 1995
    Date of Patent: April 28, 1998
    Assignee: Motorola, Inc.
    Inventor: Tadashi Usami
  • Patent number: 5732027
    Abstract: An output buffer circuit of a semiconductor memory device can produce multiple output buffer drive strengths. An electronic system including a memory device in which such an output buffer circuit is implemented can include a mechanism for enabling the output buffer drive strength to be easily selected by a user of the memory device (such as an assembler of an electronic system including the memory device) from the multiple possible drive strengths. The invention thus enables a memory device to be easily configured to have an output buffer drive strength that is compatible with a wide variety of electrical loads to be driven by the output buffers of the memory device.
    Type: Grant
    Filed: December 30, 1996
    Date of Patent: March 24, 1998
    Assignee: Cypress Semiconductor Corporation
    Inventors: Mathew R. Arcoleo, Raymond M. Leong, Derek R. Johnson
  • Patent number: 5729504
    Abstract: An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address lines and internally generates additional memory addresses. The integrated circuit memory can output data in a continuous stream while new rows of the memory are accessed. A method and circuit are described for outputting a burst of data stored in a first row of the memory while accessing a second row of the memory.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: March 17, 1998
    Assignee: Micron Technology, Inc.
    Inventor: Timothy B. Cowles
  • Patent number: 5721709
    Abstract: A decoder circuitry is provided between input signal lines and word lines. The number of the word lines is larger than the input signal lines. The decoder circuitry comprises a plurality of stages including at least an input side stage adjacent to the input signal lines and an output side stage adjacent to the word lines. Each of the plurality of stages includes plural logic circuits. The plural stages so vary as not to decrease in the number of the logic circuits when the stage approaches to the word lines so that the number of the logic circuits in the input side stage adjacent to the input signal lines is smaller than the number of the logic circuits in the output side stage adjacent to the word lines. Each of the logic circuits has a plurality of field effect transistors.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: February 24, 1998
    Assignee: NEC Corporation
    Inventor: Kazuyuki Nakamura
  • Patent number: 5721707
    Abstract: An erase voltage control circuit for an electrically erasable non-volatile memory cell having a control electrode and a first electrode. The circuit includes negative voltage generator means for generating a negative erase voltage to be supplied to the control electrode of the memory cell and means for electrically coupling the first electrode to a voltage supply. The circuit further includes control means for selectively deactivating the negative voltage generator means when a current supplied by the voltage supply to the first electrode of the memory cell reaches a predetermined value.
    Type: Grant
    Filed: January 23, 1997
    Date of Patent: February 24, 1998
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Corrado Villa, Marco Dallabora, Marcello Cane
  • Patent number: 5717632
    Abstract: A storage control circuit determines a programmed threshold voltage V.sub.tP of a storage cell in which the transistor threshold voltages V.sub.tT of the cell may overlap while the logical threshold voltages V.sub.tL remain distinct. In one embodiment, sixteen distinctive levels are stored in a storage cell within a 2.5 V range so that a single memory cell supplies four bits of information storage per cell, quadrupling the memory capacity per cell as compared to conventional single-bit storage cells. In an embodiment, a nonvolatile memory circuit includes a nonvolatile memory array with a plurality of memory cells and a plurality of decoders connected to the nonvolatile memory array. The plurality of decoders decode addresses to the nonvolatile memory array.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: February 10, 1998
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Robert B. Richart, Shyam Garg
  • Patent number: 5708599
    Abstract: A reference voltage generated in a Vref1 generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is selected by a column decoder. On the other hand, a substrate voltage generated in a Vbb generating circuit is supplied from a corresponding applied voltage selector to respective backgates of access transistors in each SRAM cell constituting a column which is not selected by the column decoder.
    Type: Grant
    Filed: August 1, 1996
    Date of Patent: January 13, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotoshi Sato, Kunihiko Kozaru
  • Patent number: 5708615
    Abstract: A semiconductor memory device with low current consumption is disclosed. A bit line selecting circuit (3) establishes electrical connection between a bit line (BL) selected during a read period and a node (N2) in response to bit line connection/selection signals (SB0 to SB4). A charge-up circuit (7) includes PMOS transistors (Q29, Q30). The PMOS transistor (Q29) has a source connected to a power supply (V.sub.DD), a drain connected to a drain of a transistor (Q10) of the bit line selecting circuit (3), and a gate receiving a read control signal (SC). The PMOS transistor (Q30) has a source connected to the power supply (V.sub.DD), a drain connected to the drain of the transistor (Q10) of the bit line selecting circuit (3), and a gate fixed at a ground level.
    Type: Grant
    Filed: September 5, 1996
    Date of Patent: January 13, 1998
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering Co., Ltd.
    Inventors: Fumihiro Ryoho, Hiroaki Kanno
  • Patent number: 5708607
    Abstract: A data read circuit of a memory includes an inverting unit, a precharging unit, a first amplifying unit, a second amplifying unit, and an output buffer unit. The inverting unit inverts data from a sense amplifier, and the precharging unit precharges a data bus line to Vcc/2. The first amplifying unit receives and amplifies the inverted data, and the second amplifying unit is commonly connected to an input terminal of the first amplifying unit to receive and amplify the signal output from the inverting unit. The output buffer unit receives, inverts and outputs the signal amplified by the first and second amplifying units.
    Type: Grant
    Filed: October 3, 1996
    Date of Patent: January 13, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Sang Hyun Lee, Ha Min Sung
  • Patent number: 5706241
    Abstract: A semiconductor memory device comprising a memory cell array of a plurality of memory cells formed and arranged on either a semiconductor substrate or a well of a first conductivity type formed on said semiconductor substrate, a plurality of voltage generating circuits for applying said memory cells voltages that are higher than the power supply voltage and different from each other and a switching circuit for selectively connecting the output nodes of said plurality of voltage generating circuits.
    Type: Grant
    Filed: March 15, 1996
    Date of Patent: January 6, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakamura, Toru Tanzawa
  • Patent number: 5706231
    Abstract: NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: January 6, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Nobuyuki Kokubo
  • Patent number: 5703803
    Abstract: A memory cell comprising a storage cell and a comparison circuit. The storage cell has a second node and a third node. The comparison circuit is coupled to the storage cell and comprises a first plurality of transistors coupled in series to a first input and a second plurality of transistors coupled in series to a second input and coupled to the first plurality of transistors by a first node and by a source voltage node. A match line coupled to the first node indicates a miss when values on the first and second inputs are different than values stored in the storage cell.
    Type: Grant
    Filed: April 29, 1996
    Date of Patent: December 30, 1997
    Assignee: Intel Corporation
    Inventors: Victor Shadan, Anurag Nigam
  • Patent number: 5703810
    Abstract: A latch/mask mechanism that is located between the sense amplifiers of a DRAM and the data bus. The latch/mask mechanism decouples the data bus from the sense amplifiers and permits innovative, time saving functionality during read and write operations. During a write operation, the latch can receive only those byte(s) or a row of bytes to be written. Corresponding mask bits are set to indicate those bytes to be written. Logic in the device transfers only those bytes in the row to be written to the sense amplifiers for writing to memory, leaving the data of remaining bytes in memory intact. Read operations are rendered more efficient by enabling logic, coupled to column select logic, to automatically transfer from the latch the byte selected by the column select logic and the adjacent byte. This time saving feature is particularly useful for computer graphics applications which utilize linear interpolation processes.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: December 30, 1997
    Assignee: Silicon Graphics, Inc.
    Inventor: Michael Nagy
  • Patent number: 5703826
    Abstract: The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
    Type: Grant
    Filed: March 18, 1996
    Date of Patent: December 30, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Glen Hush, Mike Seibert, Jeff Mailloux, Mark R. Thomann
  • Patent number: 5699297
    Abstract: The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for temporary evacuation and after the data in the area has been erased, the data evacuated to the flash memory is written into the area again.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Takamichi Kasai
  • Patent number: 5699314
    Abstract: The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: December 16, 1997
    Assignee: Micron Technology, Inc.
    Inventors: Glen Hush, Mike Seibert, Jeff Mailloux, Mark R. Thomann