Abstract: The invention provides a semiconductor memory including an address decoder, a first word line in electrical connection with an output terminal of the address decoder, a plurality of second word lines, a plurality of memory cells in electrical connection in parallel with each of the second word lines, a plurality of contacts each of which electrically connects each of the second word line to the first word line, and a compensator for signal delay among the memory cells in each of the second word lines. In accordance with the semiconductor memory, a group of the second word lines are connected to the first word line through a contact. Thus, since it is impossible for a memory cell in connection with the first word line through a defective contact to carry out writing data therein and reading data therefrom, such a memory cell can be readily, electrically found for removal.

Abstract: A semiconductor memory with an extended data output mode and the semiconductor memory includes a data output buffer, being always in enable state in the extended mode, for connecting between data output lines and an output terminal; a sense amplifier for sensing and amplifying the data read from a cell and transmitting the amplified data to inner input-output buses; a bus controller, being between the inner input-output buses and the data output lines, for switching connection between the inner input-output buses and data output lines in response to a data path control signal in order to store the data transmitted from the sense amplifier to the inner input-output buses and transmit the stored data to the data output buffer even after occurrence of a column address strobe signal; and a control signal generator for generating the data path control signal which is the combined signal of the signal gained by delaying the front of the column address strobe signal by a first delay time and the signal gained by del

Abstract: A semiconductor memory device comprising a memory cell array, a row decoder, an input/output register train, a burst counter, an input/output bus, a refresh counter and a multiplexer. The memory cell array includes a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells. The input/output register train has a plurality of registers corresponding to the bit line pairs. Each of the registers is connected to the corresponding bit line pair. The input/output bus inputs and outputs data to and from the register train in response to a signal from the burst counter. The multiplexer supplies the row decoder with an external address signal as an internal address signal. After data is transferred from any bit line pair to the register or before data is transferred from any register to the bit line pair, the multiplexer supplies the row decoder with a refresh address signal from the refresh counter in place of the external address signal.

Abstract: The non-volatile semiconductor memory disclosed includes an X-decoder and word line potential supply circuits, and a current setting/holding circuit. The X-decoder and the word line potential supply circuits set all word lines ground potential in the flash erasing operation, to a predetermined first over-erasing judgment reference potential in an "on" cell detecting operation, and to a predetermined second over-erasing judgment reference potential for judgment of over-erasing deeper than the first over-erasing judgment reference potential and, in an "on" cell specifying operation, set predetermined selected word lines to the first over-erasing judgment reference potential while setting other word lines than the selected word line to the second over-erasing judgment reference potential. The current setting/holding circuit sets the reference current in an "on" cell specifying reference current setting operation such that the result of the check by a sense amplifier is "on".

Abstract: A semiconductor memory device includes a memory cell array with each cell being connected to respective pairs of complementary bit lines, and a write circuit for writing data to the memory cells by applying complementary write signals to the complementary bit lines. The write circuit includes complementary data lines, a buffer circuit for applying complementary data signals to the data lines in response to the input data, and sense amplifier connected to the data lines and the bit lines for amplifying the data lines differential signals and for producing the complementary write signals.

Abstract: The non-volatile memory includes a word line potential control circuit in a non-volatile memory having a memory cell array, word lines, bit lines, an X decoder, a bit line selector, and a source voltage applying circuit. The word line potential control circuit is provided with a threshold voltage detection circuit and a plurality of word line potential control transistors. The threshold voltage detection circuit includes a threshold voltage holding memory cell transistor having a simultaneously processed identical structure as the memory cell transistors and disposed adjacent to the memory cell transistors so as to hold a threshold voltage after ultraviolet light erasing. The threshold voltage detection circuit detects whether a threshold voltage of the threshold voltage holding memory cell transistor is above or below a predetermined reference voltage.

Abstract: A semiconductor memory device includes a memory cell array, a redundant row memory cell array, a redundant column memory cell array and a redundant column row memory cell array. A redundant row test activation signal, a redundant column test activation signal and a multi-bit test activation signal are activated in response to signals RAS, CAS and WE and address key signals. In a redundant row test mode, a redundant word line is selectively driven in response to a row address signal. In a row column test mode, a redundant column selection line is selectively driven in response to a column address signal. In addition, data shrinking circuit is provided in order to enable a multi-bit test of redundant rows and redundant columns.

Abstract: A reference circuit for overerase correction in a flash memory includes a reference flash memory cell biased in a substantially similar manner to that of an overerased flash memory cell. The leakage current for the reference flash memory cell is preset to a tolerable level of leakage current for a maximum operating temperature of the flash memory and the reference flash memory cell tracks the temperature characteristics of the overerased flash memory cell, to avoid costly overcorrection at high temperatures.

Abstract: A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

Abstract: In an alignment structure of a main amplifier in a memory device, main amplifiers are aligned between memory cell arrays, so that the data line is shortened from the selected column switch to the main amplifier, to thereby reduce power consumption.

Abstract: Low-voltage-correcting bias circuitry for a sense amplifier includes first, second and third N-channel transistors. The channel of the first transistor couples a current mirror to the input terminal of the amplifier and the gate of the second transistor, the channel of the second transistor couples the gate of the first transistor to a reference terminal. The channel of the third transistor couples the supply voltage to the gate of the first transistor. The gate of the third transistor is coupled to a reference voltage. A P-channel transistor has a channel coupling the supply voltage to the gate of the first transistor. The gate of the P-channel transistor is coupled to a low-voltage-sensing signal. Pre-charge circuitry includes a nonvolatile memory cell and fourth, fifth and sixth N-channel transistors. The channel of the fourth transistor is in series with the channel of the memory cell. The channel of the fifth transistor couples the channel of the memory cell to the input of the sense amplifier.

Abstract: Disclosed is a semiconductor memory device which has memory cell transistors each comprising a liner source diffusion layer, a land-shaped drain diffusion layer, a gate oxide film containing a floating gate formed on the channel region between those diffusion layers, and a control gate formed on the gate oxide film. Trenches are formed in the substrate in no contact with the channel regions to isolate the cell transistors from each other.

Abstract: The present invention relates to a word driver circuit provided in a memory circuit. The word driver circuit comprises a P channel and an N channel transistor having a gate electrode commonly connected and one source or drain electrode commonly connected. The N channeltransistor has another source or drain electrode connected to a ground. A word line is connected to the commonly connected source or drain electrode of the transistors. A first selection signal, generated by decoding a first group of address signals, whose potential is either a first potential by which the N channel transistor is rendered conductive or a second potential lower than the first power supply is supplied to the gate electrodes. And a second selection signal, generated by decoding a second group of address signals, whose potential is either a third potential of the selected word line or a fourth potential equal or lower than the first power supply is supplied to another source or drain of the P transistor.

Abstract: An improved sense amplifier for receiving differential inputs and providing an output signal. A level shifting circuit for receiving differential inputs (IN and IN) is provided. A pre-amplification circuit that is coupled to the level shifting circuit provides gain to the differential outputs. A first inverter is coupled to the pre-amplification circuit and provides high voltage gain to the output signal. The first inverter includes a power port for receiving a power voltage signal and a ground port for receiving a ground signal. A second inverter that has a ground port and a power port is coupled to the pre-amplification circuit. The power port of the first and second inverters are coupled to the power voltage supply through a first transistor. Similarly, the ground port of the first and second inverters are coupled to the ground via a second transistor. The output of the second inverter is coupled to the gate of the first and second transistors and controls the first and second transistors.

Abstract: The present invention relates to a memory apparatus to be able to do write protection and aims to protect data in a specified area in a memory device not to be easily rewritten.When address signals A11 to A0 outputted from a microprocessor are written in the area 300 to 3FF, a CS signal from an address decoder for memory selection to a memory device is "enable" and it is possible to read from and write in the memory device. In the case in which the address signals are written in the area 3F0 to 3FF, the address decoder for write protection becomes "enable" and an output of an AND circuit is selected by a selector and is supplied to the memory device as a WE signal. If a write control signal is "enable", the WE signal outputted from the microprocessor is not masked by the AND circuit and it is possible to write in the memory device.

Abstract: The present invention relates to a flash memory device and pre-program only the memory cells which keep the erase state by verifying whether the memory cells are programmed before performing the pre-program operation to prevent the memory cell from being over-programmed at the time of pre-program. Accordingly, there are excellent effects in that the reliability of the device can be improved by preventing the memory cell from being over-programmed and the operation speed of the device can be improved by reducing the time required in the pre-program operation.

Abstract: A pseudo-differential sense amplifier with improved common mode noise rejection is disclosed. The sense amplifier is connected to a memory cell via an array path and generates an output signal indicative of the state of the memory cell. The sense amplifier includes an array load device connected via an array node to the array path, a reference load device connected via a reference node to a reference path, a differential stage having a first input connected to the reference node, a second input connected to the array node and an output generating the output signal. The sense amplifier further includes a balancing device, connected to the reference node, for compensating a change in signal, caused by a noise event, at the array node and, thus reducing a delay in the response of the sense amplifier when a transition in the state of the cell occurs.

Abstract: An apparatus for and method of ensuring proper transfer of data between two registers. A device driver utilizes a clock signal as an enable input before data is transferred from one register to another. This prevents a misregistration of data when delays in propagation of the clock signal exceed delays in propagation of data signals. In alternate embodiments, provision is made for bidirectional transfer by ANDing the clock signal with directional control signals to produce the enable signal. There is also a provision for implementing the concepts of the invention in connection with a shared bus interface, and in a bidirectional interface in such a manner as to ensure a lack of bus contention.

Abstract: An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.

Abstract: Exposure light from a pattern on a first surface advances through a first converging group, is then reflected at the periphery around an aperture on a first plane mirror, thereafter is reflected by a second converging group including a first concave reflecting mirror, and forms a first intermediate image of the pattern in the aperture of first plane mirror. A beam from the first intermediate image passes through a third converging group to form a second intermediate image of the pattern in an aperture of a second plane mirror. A beam from the second intermediate image is reflected by a fourth converging group including a second concave reflecting mirror, thereafter is reflected at the periphery around the aperture of second plane mirror, and then passes through a fifth converging group to form an image of the second intermediate image on a second surface. A projection optical system is arranged as described without using a beam splitter.