Abstract: A clamp circuit for a read-only-memory (ROM) device provides clamp voltages which can uniformly compensate for the parasitic capacitance on ROM word lines and improve the performance of the ROM device. The clamp circuit includes an active load, a plurality of amplifiers and a transmission gate. The amplifiers have various trip voltages and are controlled by different decoding signals for providing various clamp voltages to different word lines in the ROM device. Each amplifier is composed of a NOR gate and a transistor. The amplifier trip voltages can be easily set to desired values when designing NOR gate layout patterns without additional complicated processes being introduced into the fabrication methodology of a semiconductor integrated circuit.

Abstract: A method for fabricating a semiconductor memory device includes the steps of forming, in a semiconductor substrate of a first conductivity type, a well of a second opposite conductivity type by protecting the substrate surface except for a part where the well of the second conductivity type is to be formed, oxidizing the exposed surface of the semiconductor substrate while using the same mask pattern to form a thick oxide film on the surface of the well, and removing the thick oxide film by an etching process to form a recessed surface on the well.

Abstract: In order to provide a multi-valued DRAM with an access time comparable to ordinary binary DRAMs, a potential difference generated by a memory cell between a pair of bit-lines is delivered to N-1 sets of sense amplifiers. Each delivered potential difference is shifted by a predetermined value for each sense amplifier for classifying the potential difference into N levels. A refreshing potential for the memory cell is obtained from outputs of the sense amplifiers activated with sense amplifier activating signals having potentials predetermined for each sense amplifier.

Abstract: Bit lines includes sub-bit lines arranged corresponding to respective memory cell column groups, and also includes main bit lines MBLa and MBLb. When selecting a word line, a separation transistor is turned off, so that the main bit line is divided into two divided main bit lines, and a memory group including the selected word line and a memory cell block which is disposed at a symmetrical position with respect to the separation transistor are selected. After the separation transistor is turned off, sense amplifiers perform sensing operation. Influence against the sensing operation, which may be caused by noises due to a bit line capacitance, is prevented, and the hierarchical bit lines are accurately equalized and precharged.

Abstract: A semiconductor memory using cells with a ferroelectric capacitor having one plate connected to a bit line by a MISFET and another plate connected to a plate line. A plate line control signal is applied to a plate line of a selected row by a pulse generator. The pulse generator generates the plate line selecting signal with a predetermined pulse width after enabling a word line.

Abstract: A data storage medium comprising a substrate and a data storage layer formed on the substrate. The data storage layer comprises a fixed number of atomic layers of a magnetic material which provide the data storage layer with a magnetic anisotropy perpendicular to a surface of the data storage layer. A data magnetic field is created in the data storage layer. The data magnetic field is polarized either in a first direction corresponding to a first data value or in a second direction corresponding to a second data value. Data is stored in the data storage layer by providing a spin-polarized electron having an electron magnetic field with a direction of polarization corresponding to one of the first and the second data values, and directing the spin-polarized electron at the data magnetic field to impart the direction of polarization of the electron magnetic field to the data magnetic field.

Abstract: A non-volatile memory cell (10) is provided employing two transistors (11, 12) connected in series. A floating gate structure (13), formed with a single polysilicon deposition, is shared by each transistor (11, 12) to store the logic condition of the memory cell (10). To program and erase the memory cell (10), a voltage potential is placed on the floating gate (13) which modulates the transistors (11, 12) so only one is conducting during read operations. The gate capacitance of the transistors (11, 12) is used to direct the movement of electrons on or off the floating gate structure (13) to place or remove the stored voltage potential. The two transistor memory cell (10) couples one of two voltage potentials as the output voltage so no sense amp or buffer circuitry is required. The memory cell (10) can be constructed using traditional CMOS processing methods since no additional process steps or device elements are required.

Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).

Abstract: A film lens comprises a light transmitting base having one side and an opposite side, a plurality of concave or convex unit lenses formed on the one side of the light transmitting base, and a plurality of projections formed on the opposite side of the light transmitting base and having a profile height not smaller than the wavelength of a source light and not greater than 100 .mu.m. In this arrangement, when the film lens is placed on a smooth surface of a light guide plate of a surface light source of the edge-light type, the projections on the reverse side of the light transmitting base can secure a gap with a width not smaller than the wavelength of the source light between the film lens and the light guide plate. Thus, the source light can be uniformly distributed without hindrance throughout the light guide plate as it is totally reflected by the surface of the guide plate.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Abstract: In a semiconductor memory device including: a plurality of sub word lines, a plurality of sub word decoders each connected to one of the sub word lines, a plurality of pairs of main word lines each pair connected to a number of the sub word decoders, and a plurality of main word decoders each connected to one of the pairs of main word lines, each of the main word decoders sets voltages at a respective pair of the pairs of main word lines different from each other in a selection mode and sets the voltages at a respective pair of the pairs of main word lines the same as each other in a non-selection mode.

Abstract: A FIFO memory (4) provides serial to parallel and parallel to serial data conversion. A read frame buffer (40) and a write frame buffer (30) are coupled with a RAM array (22). Serial input data is stored temporarily into the write frame (30) of fixed width, n bits wide. Then, the entire n bit wide frame of stored serial input data is written into RAM array (22) at once in parallel. Data read in parallel from RAM array (22) is stored temporarily into the read frame (40) and thereafter provided serially to the FIFO output (53). By converting serial input to parallel input, overall chip size is reduced by reducing the number of pointers required because it is not necessary to address the RAM (22) individually when serially writing data into it. The read frame (40) coupled to the write frame (30) and to the serial input data. This allows data written into the FIFO to be immediately available and allows the read frame (40) to receive backfilled data from the write frame (30).

Abstract: A semiconductor memory device with internal self-refreshing is provided. The invented memory device has a programmable internal oscillator for controlling a self-refreshing time period. The internal oscillator obviates the need for an external signal for refreshing data stored in the device's memory cells. The pin-out configuration of the device is analogous to the pin-out configuration of an SRAM device, so that the invented device can replace an SRAM device on a circuit board. The self-refreshing time period is programmable to different time periods depending upon the intended use of the device for minimizing power consumption by the device. The oscillator provides an output pulse for incrementing an address counter which generates internal refreshing addresses and also activates a memory word line for memory cell refreshing. A comparator compares an external address and the internal refreshing address generated by the counter.

Abstract: This invention presents a new SRAM cell comprising only two MOSFETs: one is the access device for data transfer; and the other is operated as a high gain gated lateral BJT in the reverse base current mode so as to constitute the role of the storage flip-flop or latch. This invention also requires only one-sided peripheral circuitry for Read/Write function. Thus the chip area is greatly saved. In addition, the invention is fully compatible with the existing low-cost, high-yield standard CMOS process.

Abstract: A method and apparatus for emulating a high storage capacity DRAM component. The emulation involves the use of a component containing multiple DRAMs, each having a lower storage capacity than that of the emulated DRAM, but having a cumulative storage capacity greater than or equal to that of the DRAM being emulated. Emulation entails the decoding of extra bits in an address signal from a controller for the high capacity DRAM to direct the output of DRAM control signals from a decoder to the multiple DRAM component so as to activate only one of the plurality of lower density DRAMs therein. Advantageously, the invention may be implemented so as to permit migration to a next generation DRAM device without altering wiring on the printed circuit board or changing the memory controller used to access the DRAM component.

Abstract: A semiconductor memory device comprises column decoders of the number greater than the number of column addresses of a memory cell array and logical circuits of the same number as that of the column addresses. A column gate of a column is controlled by means of a logical OR between outputs from a plurality of column decoders for decoding different column addresses. As a result, even a column located at an end of the memory cell array can be accessed by means of a logical OR between outputs from a column decoder corresponding to the column and another column decoder.

Abstract: A semiconductor nonvolatile memory device including first and second bit lines, a buffer memory connected to the first and second bit lines, an electrically erasable programmable nonvolatile memory connected to the first and second bit lines, a writing latch circuit to which the first and second bit lines are connected in parallel and having a differential sensor type sense amplifier, and a switching circuit for switching the nonvolatile memory and the latch circuit to a nonconnected state at the time of operation of the buffer memory and switching the buffer memory and the latch circuit to a nonconnected state at the time of a writing or erasure operation on the nonvolatile memory.

Abstract: A projection lens unit using the principles of liquid-cooled, optical coupling is disclosed. In particular, the present invention automatically re-focusses a lens unit that is being exposed to high temperature operating conditions. The temperature rise of the optical coupling liquid changes the refractive index of the liquid, thereby changing the focussing distance of the projection lens. As a result, the picture projected onto the screen becomes unfocussed. The present invention provides a countermeasure for automatically re-focussing the picture projected on the screen. An optical coupling lens, which is one of the lens element group of the projection lens, is movably coupled to an OC housing to move along the optical axis. The volume expansion caused by the temperature rise of the optical coupling liquid is converted to a pressure change. The pressure change is used for controlling the movement of the optical coupling lens.

Abstract: A synchronous random access memory, such as a synchronous dynamic random access memory or a synchronous graphic random access memory, is responsive to command signals and includes a bank memory array. A command decoder/controller responds to command signals to initiate, in a first system clock cycle, a burst write command controlling a burst write operation to transfer multiple input data sets to the bank memory array. When the synchronous random access memory is programmed with a read latency of three or more, the command decoder/controller responds to command signals to initiate, in a second system clock cycle, a read command controlling a read operation to transfer at least one output data set from the bank memory array. One of the multiple input data sets transferred during the write operation is input into the memory device during the second system clock cycle.