Abstract: A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device comprises an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further comprises receiving means for taking in a decision signal for determining the product specification, switching signal generator means, connected to the receiving means, for producing a switching signal for changing the product specification based on the decision signal, and switching means which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.

Abstract: For a semiconductor memory device comprising, besides a redundant array, memory cells of an ordinary array in links (columns, rows) accessed by an ordinary address signal, an additional address signal of a high level activates, when the ordinary address signal indicates a preliminarily stored faulty link, a redundant circuitry activating signal for suspending operation of an ordinary link selecting circuit to select by a redundant link selecting circuit a substitution link for the faulty link. When given a low level, the additional address signal deactivates the redundant circuitry activating signal to select ordinary links by the ordinary address signal. Before the faulty link is stored, the low level serves as a test mode signal for testing the ordinary and the redundant arrays in a common mode of operation.

Abstract: A device that synchronizes an output stage of an electronic memory by enabling the output stage of the memory device after data has been retrieved from the memory, the memory chip is enabled, and output of the memory data is requested. The device also can enable the output stage of the memory regardless of whether the data has been retrieved from the memory based upon receipt of a forced activation signal, and can enable the output stage of the memory for selected bits.

Abstract: A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.

Abstract: A device including a load connected by a selection circuit to a number of bit lines, and a load connected to a reference cell, for detecting the current in the selected bit line and in the reference cell. The load connected to the bit lines comprises a transistor, and the reference load comprises two current paths, each formed by one transistor. One of the two transistors is diode-connected, and the other is switchable by a switching network connected to the gate terminal of the respective transistor, for turning it off when only one reference current path is to be enabled, and for diode-connecting it when both the reference current paths are to be enabled.

Abstract: An apparatus and method for managing a memory is disclosed. A discharging unit discharges overcharged bit lines in memory. The discharging unit discharges the bit lines after a predetermined time after the last memory access. The discharging unit also discharges the bit lines after a microprocessor comes out of a low power mode.

Abstract: The timings can be generated in synchronism with master clocks, so that it is possible to obtain the timing generating device of synchronous circuit, which is effectively applicable to a large scale integrated circuit, while facilitating the test thereof.

Abstract: A synchronous semiconductor device operates in synchronism with clock signal supplied from an external unit. The synchronous semiconductor device can be set in a first mode (a CSUS mode) and a power down mode (a PD mode) as an operation mode when a predetermined external signal (a CKE signal) is in a predetermined state.

Abstract: A DRAM includes an address registration circuit for registering an address of a row including a memory cell having poor data retention characteristic, and an entire refresh period setting circuit for setting a multiple value m of a refreshing period. The row of the registered address is refreshed in the refresh period, and other rows are refreshed in a period m times the refreshing period. Therefore, as compared with the prior art in which all the rows are refreshed in the refresh period set for the rows including the memory cell having poor data retention characteristic, power consumption can be reduced. Further, as compared with another prior art in which the refresh period setting circuit is provided for each row, the number of circuits can be reduced.

Abstract: A memory controller circuit for use in a computer system provides memory address and control signals to a single in-line memory module (SIMM) connector. The SIMM connector can hold a SIMM that has dynamic random access memories (DRAMs) mounted on one or both sides. The SIMM connector provides a channel of signals to both sides of the SIMM. A driver associated with each channel receives a memory address and control signal. Each driver either drives a buffered memory signal to the associated channel or is placed in a high impedance state, depending upon whether a SIMM is in the SIMM connector. If a SIMM is in the connector, the driver associated with one of the channels is placed in the high impedance state if it is determined that the SIMM is single-sided. A programmable disabling means provides a driver enable signal to each driver. When the driver enable signal is asserted, the corresponding driver is in an enabled state. A deasserted driver enable signal places the corresponding driver in a disabled state.

Abstract: A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read operations by input/output circuitry having an input buffer, write driver circuits, sense amplifiers, an output buffer and an output register. Data is read from individual memory blocks using a pipelined read data mode in which data accessed by a row, column and block address during a first cycle is stored in an output (pipeline) register at the beginning of the next cycle. In one embodiment all components of the data input/output circuits are located remotely from the memory blocks and paired data lines are used.

Abstract: A memory device including a memory for storing data having volatile and non-volatile capability; an access circuit for reading/writing the data stored in a volatile state at an address in said memory in accordance with an access command indicating the address; a transfer circuit for transferring the data stored in said memory from the volatile state into a non-volatile state; and a recall circuit for recalling the data stored in said memory in the non-volatile state into the volatile state, wherein said recall circuit selectively performs a recall operation for a section of said memory which includes the address before said access circuit performs a read/write operation for the data when the data at the address is stored in the non-volatile state.

Abstract: A first logic gate circuit receives an internal row strobe signal, an internal column strobe signal and a self refresh mode for providing an operation state detection signal. The operation state detection signal attains an H level when in a stand-by state and a self refresh state. A second CMOS logic gate circuit is closed when the operation state detection signal attains an H level. Therefore, an external input/output control signal is not transmitted to the internal circuit, and a through current does not flow in the CMOS logic gate independent of the level of the external input/output control signal.

Abstract: In a nonvolatile semiconductor device having a floating gate formed over a semiconductor substrate, a control gate formed over the floating gate, a source region and a drain region formed within the semiconductor substrate, an erase or write operation is carried out by Fowler-Nordheim tunneling, so that carriers such as electrons and holes are expelled from the floating gate to one of the source and drain regions. Thereafter, carriers of a channel current flowing between the source and drain regions are enhanced and injected into the floating gate, thus converging a threshold voltage of the device.

Abstract: A semiconductor memory device for serially outputting previously loaded data from an integral memory is disclosed herein. The device is configured to output head data from a predetermined location in the memory by latching the head data directly from a common bus. In a preferred embodiment the head data is latched by a single latch circuit. In a method of the invention, the head data is transferred directly from a predetermined memory address onto a common bus. A latch circuit then latches the head data from the common bus. The latched head data is next presented to an output buffer. Thereafter, data is presented in a serial form from a plurality of serial registers to the output buffer.

Abstract: A low power circuit (10) for translating logical addresses or input data to corresponding physical addresses or output data respectively. The circuit (10) includes an input latch (12), content addressable memory (CAM) (14), random access memory (RAM) (16), output latch (18), and comparator (20). The input latch (12) receives the logical address (22) and stores the logical address for at least one comparison cycle. The CAM (14) receives the logical address (22) and produces a corresponding match signal. The RAM (16) receives the corresponding match signal and produces the corresponding physical address (28). The output latch (18) receives the corresponding physical address (28) and stores the value for at least one clock cycle. The comparator (20) enables the CAM (14) and/or the RAM (16) operation only when the previous logical address does not match the current logical address (22).

Abstract: A semiconductor memory which includes a plurality of memory cells each having first and second capacitors connected in series and a field-effect transistor whose source or drain is connected to a node between the first and second capacitors. The memory cells are arranged at intersections of bit lines and word lines thereby forming a matrix. The first capacitor of each memory cell is a ferroelectric capacitor using a ferroelectric material as an insulating film. A plate electrode of the first capacitor of each memory cell is held at a first potential when the memory is operated in a first mode and the plate electrode of the first capacitor is held at a second potential when the memory is operated in a second mode. The first potential is different from the second potential.

Abstract: EEPROM for directly outputting addresses of those in which erasing failure occurs among a plurality of blocks to be erased for erasing by a plural block simultaneous erasing system to an outside of a chip and enabling a system side to directly identify the addresses thereof is provided with a plurality of cell blocks each having an array of nonvolatile memory cells, plural block simultaneous erasing control arrangement for performing cell data erasing from a plurality of cell blocks specified as to be erased for simultaneous data erasing and a block address outputting circuit for outputting, when existence of erase failure blocks is detected after block simultaneous erasing, addresses thereof to the outside of the chip.

Abstract: At the time of erasing, the erase verification is not effected but the erase voltage is repetitively applied to the source of a memory cell until it is so judged that the erase current I.sub.A flowing into the source of the memory is smaller than the reference current I.sub.B and when it is judged that the erase current I.sub.A flowing into the source of the memory cell is smaller than the reference current I.sub.B, application of the erase pulse to the source of the memory cell and the erase verification are repetitively effected. As a result, in the flash memory device, it is possible to decrease the number of times of erase verification and reduce the time required for the erasing.

Abstract: A main booster circuit generates an internal supply voltage obtained by boosting a supply voltage. A detector detects a skew in an address signal. An oscillator generates a pulse signal while the detector is detecting the skew in the address signal. An auxiliary booster circuit generates an internal supply voltage in accordance with the pulse signal from the oscillator. A row decoder selects one of a plurality of word lines in accordance with the address signal. A word line driver drives the word line selected by the row decoder, based on the internal supply voltages supplied from the main booster circuit and the auxiliary booster circuit.