Abstract: Disclosed is the FIFO buffer memory, comprising a core memory 12 having a dual port structure, for substantially storing data, first and second address decoders 13 and 14 responsive to read and write clock signals, for producing addresses indicative of directing locations in the core memory when data is written in the core memory or when the data is read from the core memory, and a status detector 15 for generating memory status signals indicating whether the data can be written in the FIFO buffer memory or whether the data can be read from the FIFO buffer memory, i.e. full and empty flags. The buffer memory can be embodied without use of complicated circuits such as address counter, address register and comparator, which can be operated at high speed and embodied with high-density integration.

Abstract: A compact, wide-angle, fast zoom lens system of high optical performance which enables photography in the range of from the wide-angle region to the telephoto region. The zoom lens system has a 1-st lens unit (G1) of positive refractive power, a 2-nd lens unit (G2) of negative refractive power, a 3-rd lens unit (G3) of positive refractive power, a 4-th lens unit (G4) of positive refractive power, and a 5-th lens unit (G5) of positive refractive power. When zooming from the wide end toward the tele end is effected, the 1-st lens unit (G1), the 2-nd lens unit (G2), the 3-rd lens unit (G3) and the 4-th lens unit (G4) are movable, while the 5-th lens unit (G5) is fixed.

Abstract: A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased when the memory cell is not being accessed. The memory cell includes a storage element capable of storing either a first data value or a second data value, a pass transistor, coupled to the storage element, and a power supply generator is coupled to the storage element. The power supply generator is configured to generate supply level voltages for the storage element so as to induce the pass transistor into a substantially reverse-biased state when the storage element is not being accessed, regardless of whether the storage element is storing the first data value or a second data value.

Abstract: An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation.

Abstract: A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative. Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.

Abstract: A non-volatile semiconductor memory with an auto-function for automatically writing or erasing data includes a logic circuit, a select circuit and a test-mode control section. The test-mode control section responds to a plurality of signals transmitted from the outside of the memory for outputting a second verify signal indicating that a verify result is normal, a third verify signal indicating that the verify result is abnormal, and a select signal for selecting an external clock signal from the outside of the memory. The logic circuit forcibly sets to a predetermined value a first verify signal output from a verify circuit on the basis of the second and third verify signals output from the test-mode control section. The select circuit selects, in a normal mode, a clock signal output from an oscillator, and selects, in a test mode, the external clock signal. The number of repetitions of retrial is set irrespective of the verify signal output from the verify circuit.

Abstract: A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines to a single ended output signal indicative of the state of the data stored in a selected memory cell connected to the complementary bit lines. The circuit is constructed to operate with low voltage swings, thereby increasing the switching speed and thus the sense speed. The sense amplifier includes power down capabilities and the ability to tristate its output terminal while in a standby mode of operation during which it is capable of reading the logic level of an input signal. In one embodiment, the output signal is latched using a simple register when the output stage goes tristated, to continue to provide a valid output signal while a subsequent sense operation is performed.

Abstract: An improved approach for breaking the bit lines of a semiconductor memory device into small pieces, referred to herein as Embedded Access Trees (EATs), is introduced. Embedded Access Trees enjoy the principal advantage of the banked approach by dividing long bit lines into several smaller bit lines to decrease the effective load which a selected cell must drive. However, EATs avoid most of the limitations of the banked approach, e.g., increased size, power and complexity. In a preferred embodiment of the invention, EATs are embedded into the existing full array and do not require additional peripheral decoders, MUXes or complex and costly global routing. For a given processing technology, the present invention permits a full memory array to be subdivided into more subarrays than the banked approach, with corresponding performance improvements.

Abstract: Flash memories are produced by a novel production method according to the invention, the method comprising removing field insulation films by an etching process using side walls provided adjacent to gate portions consisting essentially of a floating gate electrode, a control gate electrode, and an inter-gate insulation film, as part of a mask for the etching. The inventive method allows the production of higher integrated flash memories without causing damage, particularly degradation of dielectric strength, to the portion of a gate insulation film situated between part of the floating gate electrode and an impurity diffused source electrode formed in the substrate.

Abstract: A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Abstract: A memory circuit for a display apparatus is required to rewrite a display memory with a clear data as a clear data operation. During the clear data operation, an address counter produces address information for accessing the display memory in response to a clock signal that has a clock rate higher than that a clock signal which is used during a normal operation in which the display memory is rewritten with display data or subject to a data read operation.

Abstract: In order to improve area efficiency of a mask ROM, a head address is inputted from a common pad (204) only in an initial access, so that addresses are thereafter changed by an internal counter (212). Data output is carried out through the common pad (204). Wires are employed for address input and data output in common, thereby remarkably reducing the number of wires.

Abstract: The present invention relates to an input buffer used in semiconductor memory devices and more particularly to an input buffer capable of operating at a high speed by using a BiCMOS (bi-complementary metal oxide semiconductor) circuit.

Abstract: A semiconductor integrated circuit capable of changing a product specification comprises a first circuit section having a first function, a second circuit section having a second function, and active signal generator means for producing an active signal for activating either the first circuit section or the second circuit section. To change the product specification, the integrated circuit further comprises means for receiving a decision signal, switching signal generator means, connected to said receiving means, for producing a switching signal for changing the product specification according to the decision signal, and switching means for receiving the active signal and the switching signal and for supplying the active signal to either the first circuit section or the second circuit section according to the switching signal.

Abstract: A static RAM is disclosed wherein a combination logic circuit can operate at a higher speed to improve the throughput and the load such as the number of gates and/or wiring lines connected to a data output line can be reduced. The static RAM comprises a RAM cell for storing data, a differential amplifier for amplifying a signal read out from the RAM cell, a level keeping circuit for keeping a level of a signal outputted from the differential amplifier, a first output line for outputting an output signal of a kept level from the level keeping circuit upon reading accessing to the static RAM as a static output, and a second output line for outputting a state of at least one of a positive phase bit line and an inverted phase bit line of the differential amplifier upon reading accessing to the static RAM as a dynamic output. The static RAM can be suitably used with an associative storage circuit represented by a tag RAM circuit of a cache memory system and like storage circuits.

Abstract: After data is written into a desired memory cell of a memory cell array, a booster circuit verifies the threshold voltage of the memory cell in which data is written. An erase timing signal generation circuit connected to a control circuit generates a timing signal for a short period of time when a memory cell having a threshold voltage higher than the power supply voltage. An erasing voltage generation circuit applies a negative erasing voltage to the memory cell in which data is written for a short period of time according to the timing signal supplied from the erase timing signal generation circuit to slightly lower the threshold voltage of the memory cell so as to prevent the excessive writing.

Abstract: Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an alternate-metal virtual-ground (AMG) EPROM or flash memory array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

Abstract: A method for producing electrically erasable and programmable read-only memory cells with a single polysilicon level, including the use of a sacrificial layer of silicon oxide to produce a high-thickness silicon oxide layer on the active area. The active area of the cell is protected from heavy source and drain implantation in order to improve reliability.

Abstract: An integrated circuit identification device (10) includes a plurality of inverters (12-16), a first bus (24), an address bus (26), a plurality of drivers (18-22), a pre-charge circuit (28) and an identification code access (30). Each inverter (12) includes a P-channel FET (32-36) and an N-channel FET (38). An identification code is written to the device (10) by selectively breaking down the gate-well dielectric layer (112) of the N-channel FET which permanently alters the FET. When the address bus provides a read signal to the gate drivers, each N-channel FET that has been altered will be unable to turn on, thus the precharging of the P-channel FET keeps the output of the inverter at a logic "1". N-channel FETs that have not be altered will be on when the read signal is provided, thus providing a logic "0".

Abstract: There are provided a plurality of ferroelectric capacitors each of which having one of a pair of electrodes thereof connected with one terminal of a switch element which has the control terminal thereof connected with a first address selecting line. Second address selecting lines are respectively connected with the other electrodes of the ferroelectric capacitors to construct a unit memory circuit. When the switch element is turned ON by the first address selecting line, one of the second address selecting line is brought into a selecting state to feed such a voltage as to polarize the ferroelectric capacitors. The remaining address selecting lines are set to an unselect potential so that the voltage to be applied to the unselected ferroelectric capacitors coupled to the remaining address selecting lines may be about one half as high as that applied to the selected ferroelectric capacitor.