Abstract: A method of controlling on/off of a core based on a used amount of an operating core and the number of tasks in an electronic device having a multi-core, and an apparatus thereof, includes confirming a load of an operating core and the number of executable tasks at a predetermined period, determining whether the load of the operating core and the number of executable tasks meet a defined on/off condition of the multi-core, and controlling on/off of the multi-core when the load of the operating core and the number of executable tasks meet the defined on/off condition of the multi-core.

Abstract: A method and apparatus for managing power of a storage system are provided. The method comprises obtaining historical access information of a plurality of storage devices in the storage system within a time cycle, determining, according to the historical access information, a cold time period in the time cycle, forming a cold storage device for storing at least a part of cold data blocks within the cold time period, and setting power of the cold storage device to a low power mode in a time period of a subsequent time cycle corresponding to the cold time period. The apparatus is configured to implement the method. The method and apparatus effectively save power consumption of the storage system.

Abstract: A computer system is partitioned during a pre-boot phase of the computer system between a first partition and a second partition, wherein the first partition to include a first processing unit and the second partition to include a second processing unit. An Input/Output (I/O) operating system is booted on the first partition. A general purpose operating system is booted on the second partition. Network transactions are issued by the general purpose operating system to be performed by the I/O operating system. The network transactions are performed by the I/O operating system.

Abstract: In standby mode, memory contents are saved to a hard disk. After AC power has been removed by disconnecting the AC plug, when the AC power is restored the data saved on the hard disk is automatically restored into memory to set the power-saving mode back to the standby mode. When the power is turned on next, quick resumption from standby mode can be accomplished.

Abstract: A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

Abstract: A clock distribution network having a separate power supply for top levels thereof is disclosed. In one embodiment, an integrated circuit includes a clock distribution network configured to distribute a clock signal to each of a number of clock consumers. The clock distribution network is arranged in a hierarchy of levels, with each of the levels including at least one buffer, and with the upper levels being closer to a source of the clock signal and the lower levels being closer to the clock consumers. The buffers of the upper levels are coupled to receive power from a first power source, via a first power grid. The buffers of the lower levels are coupled to receive power from a second power source, separate from the first, via a second power grid.

Abstract: A display device includes a boosting power supply circuit, a logic circuit and a charge transport path. The boosting power supply circuit generates a boosted power supply voltage by boosting an analog power supply voltage. The logic circuit is responsive to a decrease in a voltage level on at least one of power supply lines to which analog and logic power supply voltages are supplied for controlling a source line drive circuitry and a gate line drive circuitry to discharge charges accumulated in the display panel. The charge transport path is configured to transport charges from a power supply line on which the boosted power supply voltage is generated to a power supply line which supplies an internal logic power supply voltage to the logic circuit in response to the decrease in the voltage level on the at least one of the first and second power supply lines.

Abstract: The disclosure provides a data access management method and a data access management apparatus which includes an enabling signal generating unit for generating an enabling signal according to a processing signal, a power supplying unit for generating a voltage signal according to the enabling signal, at least a first storage unit for storing a plurality of pieces of data and staying in a standby state or a disable state according to the voltage signal, and a first processing unit. Each piece of data respectively has an access time. The first processing unit calculates a non-access proportion of the data not been accessed for a preset time, according to the access times and then determines whether the non-access proportion is larger than a preset proportion, to generate the processing signal for controlling the at least storage unit to stay in the disable state or the standby state.

Abstract: Approaches that manage energy in a data center are provided. In one embodiment, there is an energy management tool, including an analysis component configured to determine a current energy profile of each of a plurality of systems within the data center, the current energy profile comprising an overall rating expressed as an integer value, the overall rating calculated based on a current workload usage and environmental conditions surrounding each of the plurality of systems; and a priority component configured to prioritize a routing of a workload to a set of systems from the plurality of systems within the data center having the least amount of energy present based on a comparison of the overall ratings for each of the plurality of systems within the data center.

Abstract: In an embodiment, set forth by way of example and not limitation a USB power converter for an electronic device includes a USB bus including VBUS power line, a D? data line and a D+ data line, a variable voltage converter, a processor clock, a USB transceiver coupled to the D? data line and the D+ data line, and a processor coupled to processor clock and to the USB transceiver. Preferably, the variable voltage converter has an alternating current (AC) input, a direct current (DC) output coupled to the VBUS power line, and a voltage control input responsive to a voltage control signal to provide a plurality of voltage levels at the DC output. The process is, in this example embodiment, operative to develop the control signal based upon communication from an electronic device connected to the USB bus.

Abstract: Embodiments of a multi-processor system and method for synchronization and event scheduling of multiple processing elements are generally described herein. In some embodiments, timing marks are provided to the processing elements and a start-timer command is broadcasted to the processing elements after an initial timing mark. The start-timer command instructs the processing elements to initiate an internal time reference after receipt of a next timing mark. Each of the processing elements maintains a copy of the internal time reference which may be used for synchronized event scheduling.

Abstract: Power consumption and dissipation is reduced during active display of content from an internal display buffer using a power supply topology that powers a display subsystem separately from the other components of a CPU. The power supply topology enables a processor to enter a sleep state without disabling the active display of content. The processor enters a processor sleep state when the display buffer is full and the processor components are no longer needed. The processor exits the processor sleep state when the display buffer is empty and operates in conjunction with the display subsystem to fill the buffer with more content. The processor continues to enter and exit the processor sleep states as appropriate until active display ends.

Abstract: Desktop power use behavior may be detected while a portable information handling system or any other type of battery powered information handling, system is operating on external power such as an AC adapter. The desktop power use behavior may be detected by monitoring one or more power usage parameters to detect usage characteristics that indicate a battery powered information handling system is being operated in a manner that is similar to operation of a desktop information handling system. Upon detection of desktop behavior, one or more processing devices of the information handling system may respond by taking one or more desktop use response actions.

Abstract: In response to a transfer stimulus, performance of a processing workload is transferred from a source processing circuitry to a destination processing circuitry, in preparation for the source processing circuitry to be placed in a power saving condition following the transfer. To reduce the number of memory fetches required by the destination processing circuitry following the transfer, a cache of the source processing circuitry is maintained in a powered state for a snooping period. During the snooping period, cache snooping circuitry snoops data values in the source cache and retrieves the snoop data values for the destination processing circuitry.

Abstract: The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.

Abstract: A network interface includes a physical layer device coupled to a network link. A media access control module communicates with a link partner over the network link. An energy controller monitors a link utilization level of the network link and transitions, in response to the monitoring, the media access control module and the physical layer device to a low power idle mode, wherein the low power idle mode includes periodic transmission of a plurality of refresh frames in a refresh cycle and wherein at least one of the plurality of refresh frames is modified to include at least one first data payload.

Abstract: A director node of a plurality of nodes determines a plurality of data arrays, where the plurality of data arrays have been discovered at boot time. The director node determines global metadata information, based on reading boot sectors of at least one of the plurality of data arrays discovered at boot time. A determination is made from the global metadata information as to how many data arrays had been previously configured. In response to determining that the plurality of data arrays discovered at boot time is not equal in number to the previously configured data arrays, the director node determines that all configured data arrays have not been discovered.

Abstract: A data center system management device receives power configuration information for one or more power groups. Each power group has one or more servers. The power configuration information has a power group power limit for each power group. The power budgets are sent to server control units within each power group. Messages are received from each of the server control units, the messages including information to indicate whether servers in the power groups have a power deficit or a power surplus, and a number of power units for the power deficit and power surplus for each server. The server power budgets of the one or more servers in each of the one or more power groups based on power deficits and power surpluses within each power group using a priority based reallocation mechanism.

Abstract: A server comprises a first motherboard module. The first motherboard module comprises a first motherboard, a first CPU, at least one first memory module, a chipset, input/output units, a BIOS unit and a first QPI connector. The first CPU is disposed on the first motherboard. The first memory module electrically couples with the first CPU. The chipset electrically couples with the first CPU. The input/output units electrically couple with the chipset. The BIOS unit electrically couples with the chipset. The first QPI connector electrically couples with the first CPU through a QPI bus. The first QPI connector is connected to a second motherboard module.

Abstract: A processing system with multiple processing units may support separate operating systems (OSs) in separate partitions. During an initialization process, a preboot manager in the processing system may copy software to a sequestered area of memory in the processing system. The preboot manager may also configure the processing system to hide the sequestered area of memory from a first partition of the processing system. Also, the preboot manager may use a first processing unit in the processing system to boot an OS on the first partition, and the preboot manager may transmit a boot trigger from the first processing unit to a second processing unit in the processing system. The boot trigger may cause the second processing unit to use the software in the sequestered area of memory to boot a second partition of the processing system. Other embodiments are described and claimed.