Patents Examined by Fahmida Rahman
  • Patent number: 9182810
    Abstract: The aspects enable a computing device or microprocessor to determine a low-power mode that maximizes system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. The various aspects provide mechanisms and methods for compiling a plurality of low power resource modes to generate one or more synthetic low power resources from which can be selected an optimal low-power mode configuration made up of a set of selected synthetic low power resources.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: November 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew J. Frantz, Norman S. Gargash, Tracy A. Ulmer
  • Patent number: 9170638
    Abstract: A method and apparatus are described for reducing power consumption in a processor. A micro-operation is selected for execution, and a destination physical register tag of the selected micro-operation is compared to a plurality of source physical register tags of micro-operations dependent upon the selected micro-operation. If there is a match between the destination physical register tag and one of the source physical register tags, a corresponding physical register file (PRF) read operation is disabled. The comparison may be performed by a wakeup content-addressable memory (CAM) of a scheduler. The wakeup CAM may send a read control signal to the PRF to disable the read operation. Disabling the corresponding PRF read operation may include shutting off power in the PRF and related logic.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: October 27, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganesh Venkataramanan, Emil Talpes
  • Patent number: 9171024
    Abstract: A method and apparatus for facilitating application recovery using configuration information is described. In one embodiment, a method for facilitating application recovery using configuration information includes accessing information in memory associated with an application configuration that correlates with source computer hardware for operating an application using at least one processor, identifying at least one portion that is to be restored of the application configuration using the at least one processor and applying the at least one portion of the application configuration in the memory to destination computer hardware using the at least one processor.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: October 27, 2015
    Assignee: Symantec Corporation
    Inventor: Amol Manohar Vaikar
  • Patent number: 9146760
    Abstract: Described is a technology by which independent computing functions such as corresponding to separate operating systems may be partitioned into coexisting partitions. A virtual machine manager, or hypervisor, manages the input and output of each partition to operate computer system hardware. One partition may correspond to a special purpose operating system that quickly boots, such as to provide appliance-like behavior, while another partition may correspond to a general purpose operating system that may load while the special purpose operating system is already running. The computer system that contains the partitions may transition functionality and devices from one operating system to the other. The virtual machine manager controls which computer hardware devices are capable of being utilized by which partition at any given time, and may also facilitate inter-partition communication.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: September 29, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Therron L. Powell, Jason Michael Anderson
  • Patent number: 9134784
    Abstract: Systems, methods and products are described that provide predictive power state transitions for information handling devices. One aspect includes ascertaining a power state transitioning pattern of an information handling device; responsive to a power state transition to a first lower power state at the information handling device, performing an additional power state transition to automatically transition the information handling device to a second lower power state, the second lower power state being a lower power state relative to the first lower power state; and proactively resuming the information handling device to the first lower power state responsive to a timing threshold being met; wherein the timing threshold is determined based on the power state transitioning pattern ascertained. Other embodiments are described.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: September 15, 2015
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Howard Locker, Akihisa Iwakawa, Joshua N. Novak, Nathan J. Peterson, Vincent J. DeCaro, Jason P. Parrish, Scott T. Elliott
  • Patent number: 9104393
    Abstract: A power management system embodiment of the present invention comprises a power manager with a network agent in communication over a network with a network manager. The power manager is connected to control the operating power flowing to various pieces of computer network equipment at a single site. A user is able to assign names to each control port, and the power manager maintains a list of enrolled users who have access. Many operational mode choices are possible, and each can be configured by the user while remote from the power manager. The power manager can be commanded to upload a user configuration list, and it can be commanded to accept a downloaded user configuration list.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: August 11, 2015
    Assignee: Server Technology, Inc.
    Inventors: Carrel W. Ewing, Brian P. Auclair, Mark J. Bigler, Andrew J. Cleveland, James P. Maskaly, Jay Henley Williams
  • Patent number: 9098273
    Abstract: An electronic apparatus includes a first acquisition unit configured to acquire first instruction information transmitted from an external apparatus, which instructs changing of a power state to a normal energized state, a second acquisition unit configured to acquire second instruction information transmitted from the external apparatus, which instructs changing of the power state to a power saving state, and a power state change unit configured to change the power state from the normal energized state to the power saving state based on an acquisition state of the first instruction information and the second instruction information.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 4, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Masahito Hirai
  • Patent number: 9098448
    Abstract: An information handling system is provided with an intelligent boot service which addresses and resolves unbootable system scenarios. The intelligent boot service detects and corrects adverse events before booting into the operating system. The intelligent boot service architecture is extensible to add newer events and is extensible to include extensible firmware interface (EFI) technology.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: August 4, 2015
    Assignee: Dell Products L.P.
    Inventors: Gaston M. Barajas, Shree A. Dandekar, Bogdan Odulinski
  • Patent number: 9083536
    Abstract: A circuit is for monitoring the powering of a remote device through a LAN without generating an extra biasing voltage higher than the DC power supply voltage. DC voltage used for supplying the remote device is applied to the LAN line while an AC voltage is applied to the line for monitoring whether the remote device is connected to the LAN line. The DC voltage is applied to a first or “high” terminal and the AC voltage is applied to the other or “low” terminal of the LAN line through a decoupling capacitor. This arrangement allows the supplying of the remote device with a large DC voltage compatible with a fully integrated AC signal generator, disconnection detector, and PSE controller, and enhances the reliability of the recognition of whether the powered device is connected to, or disconnected from, the LAN line.
    Type: Grant
    Filed: May 21, 2007
    Date of Patent: July 14, 2015
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Riccardo Russo, Aldo Torazzina
  • Patent number: 9081625
    Abstract: A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 14, 2015
    Assignee: DELL PRODUCTS, L.P.
    Inventors: Michael Karl Molloy, Mukund P. Khatri, Robert Wayne Hormuth
  • Patent number: 9071083
    Abstract: Super capacitor supplemented server power is described. In embodiments, a power system manager is implemented to monitor the capability of one or more power supplies to provide power for a server system. The power system manager can determine that the capability of the power supplies to provide the power is deficient, and then engage one or more super capacitor power modules to provide supplemental power for the server system to mitigate the power deficiency.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: June 30, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Shaun L. Harris, Scott Thomas Seaton, Allan J. Wenzel, Daniel G. Costello, Christian L. Belady
  • Patent number: 9048690
    Abstract: Provided is an in-vehicle power supply apparatus which supplies power to both a high-power load such as an actuator, and the CPU for controlling the high-lower load, and which is capable of preventing reduction in voltage of the CPU even when voltage of the in-vehicle power supply is momentarily reduced due to power consumption of the high-power load, and which include an auxiliary power supply having its capacity reduced so as to enable reduction of the size of the power supply apparatus.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: June 2, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroyoshi Ito
  • Patent number: 9047491
    Abstract: The subject matter herein relates to data processing and, more particularly, to encryption acceleration. Various embodiments herein provide devices and systems including a standardized encryption application programming interface embedded in firmware to perform encryption services. Some such embodiments move encryption operations away from operating system processes into firmware. As a result, encryption operations are generally accelerated.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Vincent J. Zimmer, Michael Rothman
  • Patent number: 9015456
    Abstract: A dual-mode computing system and machine-implemented method for providing an indication of an operating mode of the system. The system including a processor, a memory storing verified code, a secure memory coupled to a processor and a developer mode indicator coupled to the secure memory, wherein the processor is configured to execute verified code to perform operations comprising initiating boot up of the system. The operations further comprising accessing a developer mode state stored within the secure memory to determine whether the system is in developer mode, wherein the developer mode allows the system to execute unverified code, activating the developer mode indicator when it is determined that the system is in developer mode and locking the secure memory to ignore subsequent calls to modify the developer mode state when it is determined that the system is in developer mode.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 21, 2015
    Assignee: Google Inc.
    Inventors: Randall R. Spangler, William F. Richardson
  • Patent number: 9003210
    Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Robert J. Greiner, Xia Dai, Hung-Piao Ma
  • Patent number: 9003205
    Abstract: A system and techniques for managing power utilization in a wireless local area network are disclosed. The system can utilize an infrastructure power management module that is configured to identify and power down one or more unused wireless devices and/or dynamically reconfigure the wireless operation of one or more wireless devices to consume lower power while still operating according to network requirements.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 7, 2015
    Assignee: Symbol Technologies, Inc.
    Inventors: Rajiv Iyer, Jason Harris, Ramesh Sekhar
  • Patent number: 8996848
    Abstract: An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). The processor (130) is coupled to the on-chip boot ROM (132) and to the non-volatile security identification element (140) to selectively execute boot code depending on the non-volatile information of the non-volatile security identification element (140). Other technology such as processors, methods of operation, processes of manufacture, wireless communications apparatus, and wireless handsets are also disclosed.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: March 31, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Charles W. Brokish, Narender Madurai Shankar, Erdal Paksoy, Steve Karouby, Olivier Schuepach
  • Patent number: 8949648
    Abstract: A system and method for synchronizing clocks across a packet-switched network eliminates wander accumulation to enable precision clock distribution across a large network. In addition to standard Precision Time Protocol (PTP) synchronization messages or similar time synchronization messages, each clock regenerator stage receives a grand clock error message from the previous stage, updates this error message with its own stage clock error, and then transmits the updated grand clock error to the next stage. This enables the synchronization algorithm to compensate for the error of the previous stage, effectively locking each clock regenerator stage to the grand master clock directly.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: February 3, 2015
    Assignee: Semtech Corp.
    Inventor: Mengkang Peng
  • Patent number: 8935546
    Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: January 13, 2015
    Assignee: Intel Corporation
    Inventors: Stephen H. Gunther, Robert J. Greiner, Xia Dia, Hung-Piao Ma
  • Patent number: 8930729
    Abstract: An embodiment of the invention includes a circuit to determine the power lost between a network device and a network power supply. Using this determination, an embodiment of the network device may increase its power consumption by an amount equal to the difference between the actual cable power loss and the worst-case cable power loss. This allows the network device to draw more power than allowed by network power standards without triggering the power-limiting circuitry of the network power source or overloading the network power device. The network device can determine an operating configuration that utilizes this additional power consumption to improve performance. The network device may also determine the existence of network power device or cable fault conditions, and adjust its operating configuration as necessary. Operating configurations can include enabling additional or more powerful wired or wireless network interfaces.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: January 6, 2015
    Assignee: Aerohive Networks, Inc.
    Inventors: David Fifield, Dennis Wu