Patents Examined by Farid Khan
  • Patent number: 10266950
    Abstract: An etchant for simultaneously etching NiFe and AlN with approximately equal etch rates that comprises phosphoric acid, acetic acid, nitric acid and deionized water. Alternating layers of NiFe and AlN may be used to form a magnetic core of a fluxgate magnetometer in an integrated circuit. The wet etch provides a good etch rate of the alternating layers with good dimensional control and with a good resulting magnetic core profile. The alternating layers of NiFe and AlN may be encapsulated with a stress relief layer. A resist pattern may be used to define the magnetic core geometry. The overetch time of the wet etch may be controlled so that the magnetic core pattern extends at least 1.5 um beyond the base of the magnetic core post etch. The photo mask used to form the resist pattern may also be used to form a stress relief etch pattern.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mona M. Eissa, Yousong Zhang, Mark Jenson
  • Patent number: 10269609
    Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 23, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Darrell D. Truhitte, James P. Letterman, Jr.
  • Patent number: 10262947
    Abstract: A structure including a first semiconductor chip with front and rear surfaces and a cavity in the rear surface. A second semiconductor chip is mounted within the cavity. The first chip may have vias extending from the cavity to the front surface and via conductors within these vias serving to connect an additional microelectronic element to the active elements of the first chip. The structure may have a volume comparable to that of the first chip alone and yet provide the functionality of a multi-chip assembly. A composite chip incorporating a body and a layer of semiconductor material mounted on a front surface of the body similarly may have a cavity extending into the body from the rear surface and may have an additional microelectronic element mounted in such cavity.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 16, 2019
    Assignee: Tessera, Inc.
    Inventors: Vage Oganesian, Ilyas Mohammed, Craig Mitchell, Belgacem Haba, Piyush Savalia
  • Patent number: 10151806
    Abstract: A method and an apparatus are for the permanent magnetization of at least one ferromagnetic layer in a magnetic field sensor device deposited on a chip substrate. The method includes production of at least one resistance element on a chip substrate, deposition of at least one soft magnetic structuring element on the chip substrate; heating of the resistance element to above the blocking temperature and coupling of a preconditioning magnetic field; cooling of the resistance element to below the blocking temperature; and removal of the preconditioning magnetic field. The soft magnetic structuring element is arranged such that the coupled preconditioning magnetic field penetrates the structuring element substantially perpendicular to the chip surface and, at the location of the resistance element, generates magnetic field components parallel to the chip surface which penetrate the ferromagnetic layer of the resistance element at least in some areas.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 11, 2018
    Assignee: SENSITEC GMBH
    Inventors: Jochen Schmitt, Johannes Paul, Ronald Lehndorff, J├╝rgen Wahrhusen, Claudia Glenske
  • Patent number: 10141231
    Abstract: A method includes forming two fins extending from a substrate, each fin having two source/drain (S/D) regions and a channel region; forming a gate stack engaging each fin at the respective channel region; depositing one or more dielectric layers over top and sidewall surfaces of the gate stack and over top and sidewall surfaces of the S/D regions of the fins; and performing an etching process to the one or more dielectric layers. The etching process simultaneously produces a polymer layer over the top surface of the gate stack, resulting in the top and sidewall surfaces of the S/D regions of the fins being exposed and a majority of the sidewall surface of the gate stack still being covered by the one or more dielectric layers. The method further includes growing one or more epitaxial layers over the top and sidewall surfaces of the S/D regions of the fins.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yu Yang, Chia-Ta Yu, Kai-Hsuan Lee, Sai-Hooi Yeong, Feng-Cheng Yang
  • Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10134886
    Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: November 20, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Marian Kuruc, Juraj Vavro
  • Patent number: 10132769
    Abstract: The present invention generally relates to doped, metal oxide-based sensors, wherein the doped-metal oxide is a monolayer, and platforms and integrated chemical sensors incorporating the same, methods of making the same, and methods of using the same.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: November 20, 2018
    Assignee: VAON, LLC
    Inventors: Vladimir Dobrokhotov, Alexander Larin
  • Patent number: 10096658
    Abstract: Providing a light-emitting element emitting light in a broad emission spectrum. A combination of a first organic compound and a second organic compound forms an exciplex. The first organic compound has a function of converting triplet-excitation energy into light emission. The lowest triplet excitation level of the second organic compound is higher than or equal to the lowest triplet excitation level of the first organic compound, and the lowest triplet excitation level of the first organic compound is higher than or equal to the lowest triplet excitation level of the exciplex. Light emission from a light-emitting layer includes light emission from the first organic compound and light emission from the exciplex.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: October 9, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeyoshi Watabe, Satomi Mitsumori, Nobuharu Ohsawa, Harue Osaka, Kunihiko Suzuki, Satoshi Seo
  • Patent number: 10083927
    Abstract: A chip package structure is provided. The chip package structure includes a redistribution substrate. The chip package structure includes a first chip structure over the redistribution substrate. The chip package structure includes a first solder bump arranged between and electrically connecting the redistribution substrate and the first chip structure. The chip package structure includes a first molding layer surrounding the first chip structure. The first molding layer and the first chip structure are both spaced apart from the redistribution substrate by the first solder bump, thereby defining a gap there-between. The chip package structure includes a second chip structure over the first chip structure. The chip package structure includes a second molding layer surrounding the second chip structure. The chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump, and filled into the gap.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: September 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Chen, Li-Hsien Huang, An-Jhih Su, Hsien-Wei Chen
  • Patent number: 10084134
    Abstract: In a method for stretching a vapor deposition mask including a metal mask in which a slit is formed and a resin mask in which an opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the slit, a stretching assistance member is overlapped on one surface of the vapor deposition mask, the stretching assistance member is fixed to the vapor deposition mask in at least part of a portion in which the one surface of the vapor deposition mask and the stretching assistance member overlap with each other, and the vapor deposition mask fixed to the stretching assistance member is stretched by pulling the stretching assistance member fixed to the vapor deposition mask.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: September 25, 2018
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Katsunari Obata, Hideyuki Okamoto, Yoshiyuki Honma, Toshihiko Takeda
  • Patent number: 10079303
    Abstract: A semiconductor is provided that includes an nFET gate structure straddling over a first nanowire stack and a portion of a first SiGe layer having a first Ge content. The first nanowire stack comprises alternating layers of a tensily strained silicon layer, and a second SiGe layer having a second Ge content that is greater than the first Ge content and being compressively strained. Portions of the tensily strained silicon layers extend beyond sidewalls surfaces of the nFET gate structure and are suspended. The structure further includes a pFET gate structure straddling over a second nanowire stack and another portion of the first SiGe layer. The second nanowire stack comprises alternating layers of the tensily strained silicon layer, and the second SiGe layer. Portions of the second SiGe layers extend beyond sidewalls surfaces of the pFET gate structure and are suspended.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: September 18, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10074736
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an electrode, and an insulating portion. The semiconductor layer has a first surface. The electrode is provided on the first surface of the semiconductor layer. The insulating portion includes a first layer and a second layer. The first layer covers the electrode on the first surface of the semiconductor layer and has a first internal stress along the first surface. The second layer is provided on the first layer and has a second internal stress in a reverse direction of the first internal stress.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: September 11, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiharu Takada
  • Patent number: 10068906
    Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 10043875
    Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Bahman Hekmatshoartabari
  • Patent number: 10043966
    Abstract: A semiconductor device includes a lower insulating layer on a substrate, a lower wiring layer extending on the lower insulating layer, a lower surface of at least a part of the lower wiring layer being covered by the lower insulating layer, a plurality of via plugs extending in a first direction on the lower wiring layer, the plurality of via plugs including a real via plug and a first dummy via plug connected to the part of the lower wiring layer covered by the lower insulating layer, and an upper wiring layer overlapping the lower wiring layer and extending in a second direction different from the first direction on the real via plug, the upper wiring layer not overlapping the dummy via plug.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hoon Bak, Kyung-tae Nam, Yong-jae Kim, Da-hye Shin
  • Patent number: 10043805
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 7, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Pierre Morin, Nicolas Loubet
  • Patent number: 10038121
    Abstract: A light emitting diode including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, and a Bragg reflector structure. The emitting layer is configured to emit a light beam and is located between the first-type semiconductor layer and the second-type semiconductor layer. The light beam has a peak wavelength in a light emitting wavelength range. The first-type semiconductor layer, the emitting layer, and the second-type semiconductor layer are located on a same side of the Bragg reflector structure. A reflectance of the Bragg reflector structure is greater than or equal to 95% in a reflective wavelength range at least covering 0.8X nm to 1.8X nm, and X is the peak wavelength of the light emitting wavelength range.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: July 31, 2018
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting
  • Patent number: 10038067
    Abstract: A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Suyog Gupta, Bahman Hekmatshoartabari
  • Patent number: 10037885
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao