Abstract: A quantum dot electronic device comprises a first encapsulation layer, a first electrode disposed on the first encapsulation layer, a quantum dot pattern disposed on the first electrode, a second electrode disposed on the quantum dot pattern and a second encapsulation layer disposed on the second electrode. The quantum dot pattern may be formed by an intaglio transfer printing method, where the method comprises forming a quantum dot layer on a donor substrate, picking up the quantum dot layer using a stamp, putting the quantum dot layer into contact with an intaglio substrate using the stamp and separating the stamp from the intaglio substrate. Using the quantum dot transfer printing method, a subminiature quantum dot pattern can be transferred at a high transfer rate. Accordingly, a highly integrated quantum dot electronic device exhibiting excellent performance and a high integrated quantum dot light emitting device with an ultrathin film can be realized.

Abstract: An imaging device having a three-dimensional integration structure is provided. A first structure including a transistor including silicon in an active layer or an active region and a second structure including an oxide semiconductor in an active layer are fabricated. After that, the first and second structures are bonded to each other so that metal layers included in the first and second structures are bonded to each other; thus, an imaging device having a three-dimensional integration structure is formed.

Abstract: A display device includes a pixel substrate in which a plurality of wirings and a plurality of switching elements are formed. The pixel substrate includes an organic insulating film formed over the substrate, a first wiring and a second wiring arranged in parallel on the organic insulating film, a trench formed in the organic insulating film between the first wiring and the second wiring, and a protection film formed to cover the first wiring, the second wiring, and the trench.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. The device structure includes an intrinsic base, an emitter having a vertical arrangement relative to the intrinsic base, and a collector having a lateral arrangement relative to the intrinsic base. The device structure may be fabricated by forming the intrinsic base and the collector in a semiconductor layer, and epitaxially growing the emitter on the intrinsic base and with a vertical arrangement relative to the intrinsic base. The collector and the intrinsic base have a lateral arrangement within the semiconductor layer.

Abstract: A first conductive pattern is disposed on a substrate. A first conductive pattern includes a first element mount portion and a first wire connection portion. A second conductive pattern is disposed on the substrate to be spaced apart from the first conductive pattern. The second conductive pattern includes a second element mount portion and a groove. The second element mount portion has a first side, a second side substantially orthogonal to the first side, and a third side substantially orthogonal to the first side and substantially parallel to the second side. The groove extends substantially parallel to the first side. A rectangular first light emitting element is disposed on the first element mount portion. A rectangular second light emitting element is disposed on the second element mount portion adjacent to the first light emitting element. A wire connects the second light emitting element to the first wire connection portion.

Abstract: A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.

Abstract: Semiconductor devices are provided. A semiconductor device includes a stack of alternating insulation layers and gate electrodes. The semiconductor device includes a channel material in a channel recess in the stack. The semiconductor device includes a charge storage structure on the channel material, in the channel recess. Moreover, the semiconductor device includes a gate insulation layer on the channel material. The gate insulation layer undercuts a portion of the channel material. Related methods of forming semiconductor devices are also provided.

Abstract: A semiconductor structure includes a substrate including a first side and a second side opposite to the first side; a first via extending through the substrate; a second via extending through the substrate; and a metallic structure disposed between the first via and the second via, wherein the first via is isolated from the second via by the metallic structure, the first via and the second via are configured to connect to a signal source or transmit a signal, and the metallic structure is configured to connect to a power or a ground.

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract: A light detection device includes: a TFT having a semiconductor layer supported on a substrate, a source electrode, a drain electrode, and a gate electrode; a photodiode having a bottom electrode electrically connected to the drain electrode, a semiconductor laminate structure, and a top electrode; and an electrode made of the same conductive film as the bottom electrode and arranged on the semiconductor layer with an insulating layer interposed therebetween.

Abstract: An image sensor including a semiconductor layer. A light absorber layer couples with the semiconductor layer at a pixel of the image sensor and absorbs incident light to substantially prevent the incident light from entering the semiconductor layer. The light absorber layer heats a depletion region of the semiconductor layer in response to absorbing the incident light, creating electron/hole pairs. The light absorber layer may include one or more narrow bandgap materials.

Abstract: A method for producing a thin-film semiconductor body is provided. A growth substrate is provided. A semiconductor layer with funnel-shaped and/or inverted pyramid-shaped recesses is epitaxially grown onto the growth substrate. The recesses are filled with a semiconductor material in such a way that pyramid-shaped outcoupling structures arise. A semiconductor layer sequence with an active layer is applied on the outcoupled structures. The active layer is suitable for generating electromagnetic radiation. A carrier is applied onto the semiconductor layer sequence. At least the semiconductor layer with the funnel-shaped and/or inverted pyramid-shaped recesses is detached, such that the pyramid-shaped outcoupling structures are configured as projections on a radiation exit face of the thin-film semiconductor.

Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.

Abstract: The present disclosure provides a light-emitting device. The light-emitting device comprises: a substrate; an intermediate layer on the substrate; a first window layer comprising a first semiconductor optical layer on the intermediate layer and a second semiconductor optical layer on the first semiconductor optical layer; and a light-emitting stack on the second semiconductor optical layer; wherein a difference between the lattice constant of the intermediate layer and the lattice constant of the first semiconductor optical layer is greater than 2.3 ?.

Abstract: Methods of forming packages include forming an encapsulant laterally encapsulating a die over an active surface of the die. The active surface has an electrical pad. A first opening is formed through the encapsulant to the electrical pad. In some embodiments the first opening is formed using a photolithographic technique. In some embodiments the first opening is formed using a temporary pillar by forming the temporary pillar over the electrical pad, forming the encapsulant, and then exposing and removing the temporary pillar. A conductive pattern is formed over the encapsulant including a via formed in the first opening to the electrical pad of the die's active surface. In some embodiments, a dielectric layer is formed over the encapsulant, and the conductive pattern is over the dielectric layer. Embodiments may include forming additional dielectric layers and conductive patterns.

Abstract: The silicon nitride layer 910 formed by plasma CVD using a gas containing a hydrogen compound such as silane (SiH4) and ammonia (NH3) is provided on and in direct contact with the oxide semiconductor layer 905 used for the resistor 354, and the silicon nitride layer 910 is provided over the oxide semiconductor layer 906 used for the thin film transistor 355 with the silicon oxide layer 909 serving as a barrier layer interposed therebetween. Therefore, a higher concentration of hydrogen is introduced into the oxide semiconductor layer 905 than into the oxide semiconductor layer 906. As a result, the resistance of the oxide semiconductor layer 905 used for the resistor 354 is made lower than that of the oxide semiconductor layer 906 used for the thin film transistor 355.

Abstract: A packaged semiconductor device includes a communication pad formed in a side surface, which is operatively coupled to a communication circuit so as to enable the establishing of a wireless communication channel to an adjacently positioned packaged semiconductor device. The communication pad may be formed upon cutting a block including the packaged semiconductor device and an appropriately positioned and dimensioned conductor.

Abstract: A semiconductor device includes a first barrier layer having a barrier property against oxygen and hydrogen over a substrate, a first insulator over the first barrier layer, a second insulator over the first insulator, a third insulator over the second insulator, a transistor including an oxide semiconductor over the third insulator, a fourth insulator including an oxygen-excess region over the transistor, and a second barrier layer having a barrier property against oxygen and hydrogen over the fourth insulator. The transistor includes a first conductor with oxidation resistance, a second conductor with oxidation resistance, and a third conductor with oxidation resistance, the second insulator includes a high-k material, the first barrier layer and the second barrier layer are in contact with each other in an outer edge of a region where the transistor is provided, and the transistor is surrounded by the first barrier layer and the second barrier layer.