Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract: This disclosure discloses a method for making a light-emitting device, comprising steps of: providing a substrate; forming a light-emitting stack on the substrate; forming a first layer on the light-emitting stack; providing a permanent substrate; forming a second layer on the permanent substrate; bonding the first layer and the second layer to form a bonding layer to connect the substrate and the permanent substrate; wherein a refractive index of the bonding layer decreases from the light-emitting stack toward the permanent substrate.

Abstract: An electrostatic discharge device includes a power clamping circuit and an isolation circuit. The power clamping circuit includes a first Zener diode and a second Zener diode. A cathode of the first Zener diode is coupled to a first power supply line. An anode of the first Zener diode is coupled to an anode of the second Zener diode. A cathode of the second Zener diode is coupled to a second power supply line. The isolation circuit includes a first isolation diode and a second isolation diode. A cathode of the first isolation diode is coupled to the first power supply line. An anode of the first isolation diode is coupled to a cathode of the second isolation diode and a circuit being protected. An anode of the second isolation diode is coupled to the second power supply line.

Abstract: A method of fabricating a pixelated imager and structure including a substrate with a bottom contact layer and active element blanket layers deposited on the bottom contact layer. The blanket layers are separated into an array of active elements with trenches isolating adjacent active elements in the array. A dielectric passivation/planarization layer is positioned over the array of active elements. An array of active element readout circuits overlies the passivation/planarization layer above the trenches with one active element readout circuit coupled to each active element of the array of active elements. Each active element and coupled active element readout circuit defines a pixel and the array of active elements and the coupled array of active element readout circuits defines a pixelated imager, and the readout circuit coupled to each active element includes at least one TFT with an active channel comprising a metal-oxide semiconductor material.

Abstract: A method of manufacturing a fan out wafer level package comprises: preparing conductive projections on an upper surface of a chip; mounting the chip on a carrier with the upper surface of the chip facing upwards; plastic packaging the chip to form a plastic packaging body with tops of the conductive projections being disposed outside the plastic package body; and implementing a redistribution line processing on the plastic package body. With this method, chips can be made small and thin and the manufacturing processes can be simplified.

Abstract: In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material extending from a first major surface. An n-type field stop region extends from a second major surface into the region of semiconductor material. A p+ type polycrystalline semiconductor layer is disposed adjacent to the field stop region and provides an emitter region for the IGBT. An embodiment may include a portion of the p+ type polycrystalline semiconductor being doped n-type.

Abstract: Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and a projecting portion PJ2 are provided in an end portion PU of a socket terminal STE1. Thus, it is possible to enable contact between a lead and the socket terminal STE in which a large current is caused to flow, at two points by a contact using the projecting portion PJ1 and by a contact using the projecting portion PJ2, for example. As a result, the current flowing from the socket terminal STE1 to the lead flows by being dispersed into a path flowing in the projecting portion PJ1 and a path flowing in the projecting portion PJ2. Accordingly, it is possible to suppress increase of temperature of a contact portion between the socket terminal STE1 and the lead even in a case where the large current is caused to flow between the socket terminal STE1 and the lead.

Abstract: A micromechanical component includes a sensor chip and a cap chip connected to the sensor chip. A cavity is formed between the sensor chip and the cap chip. The sensor chip has a movable element situated in the cavity. The cap chip has a wiring level containing an electrically conductive electrode. The cap chip has a getter element situated in the cavity.

Abstract: A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern.

Abstract: After forming a seed layer over a first end of a sacrificial semiconductor layer composed of silicon germanium, a remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the seed layer that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

Abstract: A fin type ESD protection device includes at least one first fin, at least one second fin, and at least one gate structure. The first fin is disposed on a semiconductor substrate, and a source contact contacts the first fin. The second fin is disposed on the semiconductor substrate, and a drain contact contacts the second fin. The first fin and the second fin extend in a first direction respectively, and the first fin is separated from the second fin. The gate structure is disposed between the source contact and the drain contact. The first fin is separated from the drain contact, and the second fin is separated from the source contact.

Abstract: A semiconductor device includes a substrate including a plurality of transistor devices formed thereon, at least an epitaxial structure formed in between the transistor devices, and a tri-layered structure formed on the epitaxial structure. The epitaxial structure includes a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The tri-layered structure includes an undoped epitaxial layer, a metal-semiconductor compound layer, and a doped epitaxial layer sandwiched in between the undoped epitaxial layer and the metal-semiconductor compound layer. The undoped epitaxial layer and the doped epitaxial layer include at least the second semiconductor material.

Abstract: A magnetic tunnel junction cell includes a first electrode having an axis extending in a direction substantially perpendicular to an active surface of a substrate. The magnetic tunnel junction further includes a fixed layer, a U-shaped free layer, a tunnel layer sandwiched between the fixed layer and the U-shaped free layer and a second electrode embedded in the U-shaped free layer. The fixed layer, the tunnel layer and the U-shaped free layer are disposed between the first electrode and the second electrode and constitute a magnetic tunnel junction. The tunnel layer may also be U-shaped.

Abstract: A system and/or method for utilizing MEMS switching technology to operate MEMS sensors. As a non-limiting example, a MEMS switch may be utilized to control DC and/or AC bias applied to MEMS sensor structures. Also for example, one or more MEMS switches may be utilized to provide drive signals to MEMS sensors (e.g., to provide a drive signal to a MEMS gyroscope).

Abstract: A resistive random access memory including a first electrode, a separating medium, a resistance changing layer and a second electrode is disclosed. The first electrode has a mounting face. The separating medium is arranged on the first electrode and forms a through hole. A part of the first electrode is not covered by the separating medium. The separating medium has a first dielectric. The resistance changing layer extends along the part of the first electrode as well as along an inner face and the second face of the separating medium. The resistance changing layer has a second dielectric having a dielectric constant larger than a dielectric constant of the first dielectric by 2 or less. The second electrode is arranged on the resistance changing layer. In this arrangement, the problem of unstable forming voltage of the conventional resistive random access memory can be solved.

Abstract: In a method for stretching a vapor deposition mask including a metal mask in which a slit is formed and a resin mask in which an opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the slit, a stretching assistance member is overlapped on one surface of the vapor deposition mask, the stretching assistance member is fixed to the vapor deposition mask in at least part of a portion in which the one surface of the vapor deposition mask and the stretching assistance member overlap with each other, and the vapor deposition mask fixed to the stretching assistance member is stretched by pulling the stretching assistance member fixed to the vapor deposition mask.

Abstract: A semiconductor device carrier tape with image sensor detectable dimples is disclosed. The dimpled carrier tape is formed of a flexible strip of material. A plurality of pockets are disposed spaced apart along the length of the flexible strip of material. Each pocket is configured to hold a semiconductor device. A dimple is formed in each of the plurality of pockets where each dimple has a peripheral edge and a bottom surface. Detection of the dimple by an image sensor facilitates alignment of a semiconductor device with the pocket and precise placement of the semiconductor device in the pocket.

Abstract: A method of making electronic packages includes providing a leadframe strip that includes a plurality of leadframes, wherein the leadframes comprise a plurality of leads, etching a surface of each of the leadframes to form an opening, wherein each of the leads has a lead tip that connects to a die paddle within the opening, isolating each of the leads from the die paddle, adhering a tape to a bottom side of the leadframe strips, leads, and die paddle, attaching a die to the die paddle, placing ball bumps on each of the lead tips, and connecting the die to the ball bumps.

Abstract: A hetero-substrate, a nitride-based semiconductor light emitting device, and a method of manufacturing the same are provided. The hetero-substrate may include a substrate including a silicon semiconductor, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including a nitride semiconductor, a second semiconductor layer disposed on the first semiconductor layer and including a first conductive type nitride semiconductor having a first doping concentration, and a stress control structure disposed between the first semiconductor layer and the second semiconductor layer and including at least one stress compensation layer and at least one third semiconductor layer including a first conductive type nitride semiconductor having a second doping concentration that is the same or lower than the first doping concentration.

Abstract: Semiconductor devices are provided. The semiconductor device includes a bit line contact plug and a storage node contact plug electrically connected to an active region of a substrate. A bit line structure is disposed on the bit line contact plug to extend in a first direction. The bit line structure is disposed in a trench pattern that intrudes into a side of the storage node contact plug. Related methods and systems are also provided.