Abstract: This document describes techniques and apparatuses that enable determining expected hash-values in functions with control flow. A computing device receives a function comprising function instructions within at least three basic blocks connected via multiple execution paths. Hash-input instructions are inserted within a plurality of the basic blocks that indirectly force hash values at the respective insertion points. Hash values at ends of the plurality of the basic blocks are set to a canonical value and an expected hash-value and hash input-values are calculated using a hash function. By using the canonical value and the hash input-values, the expected hash-value is the same regardless of which execution path is executed.

Abstract: According to certain general aspects, the present embodiments relate generally to securing communication between ECUs. Example implementations can include a method of securely transmitting Controller Area Network (CAN) protocol frames via a CAN controller.

Abstract: A method for controlling an application instance to be online or offline includes: acquiring target indication information, the target indication information including an identification of a target application instance; according to the target indication information and stored target instances, determining an online or offline control instruction of the target application instance, wherein the target instances including application instances that are started and are in an offline state; and according to the online or offline control instruction of the target application instance, controlling the target application instance to be online or offline.

Abstract: An electronic device for handling a performance bottleneck of a system and an operating method thereof are provided. The electronic device includes a processor and a memory configured to store at least one instruction executable by the processor, wherein the processor, as a response to executing the at least one instruction, may determine, from a point in time corresponding to a start of a predetermined task, whether a threshold time preset for the task arrives, stop determining whether the threshold time has arrived in response to the task terminating prior to the threshold time arriving, and control one or more of resources for performing a task in response to the threshold time arriving prior to the task terminating.

Abstract: Embodiments described herein are generally related to a method and a system for constructing and delivering a pulse to perform an entangling gate operation between two trapped ions during a quantum computation, and more specifically, to a method of demodulating and spline interpolating a pulse that can be practically implemented in the system while increasing the fidelity of the entangling gate operation, or the probability that at least two ions are in the intended qubit state(s) after performing the entangling gate operation between the two ions.

Abstract: A data transfer instruction is provided which specifies register addressing information for identifying a target portion of the register storage. In response to the data transfer instruction, instruction decoding circuitry controls processing circuitry to perform a data transfer operation to transfer data to or from the target portion of the register storage. The register addressing information includes at least: a base register identifier identifying a base register of the register storage for storing a base value; and an immediate value specified in an encoding of the data transfer instruction, the immediate value representing a value to be added to the base value to provide an index value for selecting the target portion of the register storage. This can be useful to provide an instruction set architecture which supports code that is scalable to variable data structure sizes, and which supports loop unrolling.

Abstract: A method includes receiving, at a storage client, an input/output (I/O) request from a mainframe application, the input/output (I/O) request being pursuant to a first protocol, the first protocol being a proprietary, mainframe protocol. The storage client may include a plurality of drivers, each driver being associated with a respective one of a plurality of data sources. A first one of the plurality of data sources that is suitable for addressing the I/O request is identified, it being configured to communicate using a second protocol, inconsistent with the first. Configuration data associated with the respective driver of the identified data source is accessed and used to convert the I/O request to a corresponding capability of the identified data source. The I/O request is executed on the identified data source, using the corresponding capability pursuant to the second protocol, and data is received from the identified data source, in response to the I/O request.

Abstract: An authentication and information system for use in a surgical stapling system includes a microprocessor configured to demultiplex data from a plurality of components in the surgical system. The authentication and information system can include one wire chips and a coupling assembly with a communication connection.

Abstract: Techniques are disclosed for the use of fused vector processor instructions by a vector processor architecture. Each fused vector processor instruction may include a set of fields associated with individual vector processing instructions. The vector processor architecture may implement local buffers facilitating a single vector processor instruction to be used to execute each of the individual vector processing instructions without re-accessing vector registers between each executed individual vector processing instruction. The vector processor architecture enables less communication across the interconnection network, thereby increasing interconnection network bandwidth and the speed of computations, and decreasing power usage.

Abstract: A non-transitory computer-readable storage medium storing an arithmetic operation program that causes at least one computer to execute a process, the process includes searching for first order information such that an evaluation value is updated as a generation progresses by using an evolutionary algorithm for a first individual that is a target of a combinatorial optimization process which includes an array search, the individual including the first order information; generating a first array by using the first order information; converting the first array into a QUBO format; and searching for a combination by using the converted first array.

Abstract: An information handling system includes a processor having a first data storage device in a first memory tier, a second data storage device in a second memory tier, and a tiering manager. The first tier exhibits first data storage attributes and the second tier exhibits second data storage attributes. The tiering manager receives first memory access information from the first data storage device and second memory access information from the second data storage device, makes a determination that a first performance level of the information handling system when first data is stored in the first data storage device can be improved to a second performance level of the information handling system by swapping the first data to the second data storage device based upon the first memory access information and the second memory access information, and swaps the first data to the second data storage device in response to the determination.

Abstract: A computing device includes: a housing defining an exterior of the computing device; a controller supported within the housing; a first communication port disposed on the exterior; a second communication port disposed on the exterior; a port-sharing subsystem supported within the housing, having (i) a first state to connect the controller with the first communication port, exclusive of the second communication port, and (ii) a second state to connect the controller with the first communication port and the second communication port; the controller configured to: detect engagement of an external device with the first communication port; obtain connection parameters from the external device; based on the connection parameters, set the port-sharing subsystem in either the first state or the second state; and establish a connection to the external device via the port-sharing subsystem and the first communication port.

Abstract: A circuit can include a closed loop bus line having a plurality of connections. The circuit can include a plurality of integrated circuits disposed on the close loop bus line at a respective connection of the plurality of connections. One or more of the integrated circuits can be configured to drive a signal on the closed loop bus line. The closed loop bus line can be configured to prevent signal reflection. For example, in certain embodiments, there are no termination resistors at any of the terminations to reduce size, weight, and/or part count of the circuit.

Abstract: An embodiment of the present invention relates to physical interfaces, especially those used on consumer electronics devices. A processor, in which an embodiment of the disclosed invention is deployed, includes a physical interface for connecting to and communicating with a peripheral device, the peripheral device being configured to operate according to a standard communications protocol or to a different protocol which is adapted to have a more bandwidth-efficient performance. The processor detects which of the two protocols the attached peripheral device uses and configures the physical interface to operate according to the detected protocol. An embodiment of the invention allows for new, bandwidth-efficient communications protocols to be executed across existing standardized physical interface hardware, thereby allowing for easier acceptance of the new protocols within the consumer electronics industry.

Abstract: Sparse matrix operations using processing-in-memory is described. In accordance with the described techniques, a processing-in-memory component of a memory module receives a request for a vector element stored at a first location in memory of the memory module. The processing-in-memory component identifies an index value for a non-zero element in a sparse matrix using a representation of the sparse matrix stored at a second location in the memory. The processing-in-memory component then outputs a result that includes the vector element by retrieving the vector element from the first location in memory using the index value.

Abstract: A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.

Abstract: An apparatus includes logic circuitry that selects a retag transaction identifier for an original transaction identifier of an incoming transaction request, based on a plurality of sub-groups of retag tracking data. Each sub-group of retag tracking data is associated with a corresponding sub-group of retag transaction identifiers in a group of retag transaction identifiers. The logic circuitry retags the incoming transaction request with the selected retag transaction identifier (ID) by replacing the original transaction identifier associated with the incoming transaction request and sends the retagged incoming transaction request to a target. A returned response is received from the target. The retag transaction ID in the returned response is removed and replaced with the original transaction ID before being sent as a reply to the requesting unit. Associated methods are also presented.

Abstract: Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.

Abstract: A network adapter includes a network interface, a bus interface, a hardware-implemented data-path and a programmable Data-Plane Accelerator (DPA). The network interface is to communicate with a network. The bus interface is to communicate with an external device over a peripheral bus. The hardware-implemented data-path includes a plurality of packet-processing engines to process data units exchanged between the network and the external device. The DPA is to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path.

Abstract: A data transmission control device is provided. The data transmission control device is disposed in a chip that includes a Peripheral Component Interconnect Express (PCIe) interface, and the data transmission control device is coupled to a memory that includes a block. The data transmission control device includes: a control circuit, a PCIe interface controller, and an address monitoring circuit. The PCIe interface controller is configured to receive a data. The address monitoring circuit is configured to issue an interrupt to the control circuit when the data is written to the block.