Patents Examined by Farley Abad
  • Patent number: 10380060
    Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: August 13, 2019
    Assignee: Etron Technology, Inc.
    Inventor: Richard Dewitt Crisp
  • Patent number: 10382224
    Abstract: A control device and corresponding motor vehicle for connecting a CAN bus to a radio network, having the following features: the control device includes a wireless controller, a microcontroller, a first CAN transceiver and a second CAN transceiver; the microcontroller is connected, on the one hand, to the wireless controller and, on the other hand, to the CAN transceivers; the first CAN transceiver is connected to the second CAN transceiver; the first CAN transceiver is configured in such a manner that it suppresses transmission via the CAN bus and supports reception via the CAN bus in a normal mode and supports transmission and reception in a diagnostic mode; and the second CAN transceiver is configured in such a manner that it changes the first CAN transceiver from the normal mode to the diagnostic mode when the second CAN transceiver receives a wake-up frame via the CAN bus.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 13, 2019
    Assignee: Dr. Ing. h.c. F. Porsche Aktiengesellschaft
    Inventors: Timo Maise, Paul Behrendt, Kai Schneider
  • Patent number: 10366040
    Abstract: A wearable device includes a device carrier, a device core unit, a first universal serial bus (USB) interface, a second USB interface, and a signal path selection unit. The device carrier is configured to carry the device core unit, the first USB interface, the second USB interface, and the signal path selection unit of the wearable device; the device core unit is configured to perform a core function of the wearable device; the first USB interface and the second USB interface are configured to connect to an external device; the signal path selection unit is configured to control a signal path between the first USB interface and the device core unit or a signal path between the first USB interface and the second USB interface to be connected.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 30, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liangguang Xu, Nannan Li, Dong Chen, Xin Lv
  • Patent number: 10366033
    Abstract: Described are systems, methods and computer-program product for replacing a prior input/output (I/O) module and terminal board with a universal I/O device by providing software based instructions and configuration settings for the installer. The method includes provisions for new wiring changes or harnesses as well as preset adapters, converting prior device configuration settings from an I/O module, pack, and/or terminal board to new configuration settings for a programmable I/O device, generating a wiring chart for any wiring changes based on the settings, and displaying the information for the installer and/or programmer's use. This allows a universal I/O device capable of each channel having different operating modes to replace one or more of a mixture of several types of dedicated I/O modules.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: July 30, 2019
    Assignee: General Electric Company
    Inventors: Daniel Milton Alley, Roy Anthony Carter, Joshua Sherman
  • Patent number: 10366026
    Abstract: A system comprises a data storage, a decompression accelerator configured to decompress compressed data and thereby generate decompressed data, and a direct memory access (DMA) engine coupled to the data storage and the decompression accelerator. The DMA engine comprises a buffer for storage of a plurality of descriptors containing configuration parameters for a block of compressed data to be retrieved from the data storage and decompressed by the decompression accelerator, wherein at least one of the descriptors comprises a threshold value. The DMA engine, in accordance with one or more of the descriptors, is configured to read compressed data from data storage and transmit the threshold value and the compressed data to the decompression accelerator. The decompression accelerator is configured to decompress the compressed data until the threshold value is reached and then to abort further data decompression and to assert a stop transaction signal to the DMA engine.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: July 30, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Andrea Olgiati, Nathan Binkert
  • Patent number: 10360174
    Abstract: A universal serial bus circuit including a power circuit and a terminating circuit is provided. The power circuit provides a differential signal. The terminating circuit is coupled to the power circuit. The terminating circuit receives the differential signal through the first signal output terminal and the second signal output terminal, and the terminating circuit includes a first load circuit and a second load circuit. When the universal serial bus circuit is operated in a handshake mode, the terminating circuit receives the differential signal through the first load circuit and the second load circuit, and outputs a pulse signal through the first signal output terminal and the second signal output terminal. When the universal serial bus circuit is operated in a normal mode, the terminating circuit receives the differential signal through the first load circuit, and outputs a data signal through the first signal output terminal and the second signal output terminal.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 23, 2019
    Assignee: VIA LABS, INC.
    Inventors: Hsiao-Chyi Lin, Yi-Shing Lin
  • Patent number: 10353841
    Abstract: Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at least one track in a metal layer. The method includes selecting an already routed original signal path to be optimized, modifying at least one original routing parameter, creating an alternative signal path based on the modified routing parameter value, determining at least one timing value describing the delay and signal integrity of the alternative signal path and signal integrity, and replacing the already routed original signal path by the alternative signal path based on the timing value indicating that the alternative signal path complies with predefined constraints related to the delay and signal integrity.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lukas Daellenbach
  • Patent number: 10346078
    Abstract: A method according to one embodiment includes instructing a first tape drive to load a parent tape medium, and instructing the first tape drive to retrieve identification (ID) information about the parent tape medium from metadata stored (saved) thereon. The first tape drive is instructed to write a first file part of a file to the parent tape medium. Information about the file and information about the first file part are written to the parent tape medium as metadata. A second tape drive is instructed to load and retrieve ID information about a child tape medium from metadata stored thereon. The second tape drive is instructed to write one or more subsequent file parts of the file to the child tape medium. The first tape drive is instructed to write the ID information about the child tape medium and attribute information about the one or more subsequent file parts stored to the child tape medium as metadata to the parent tape medium.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Tsuyoshi Miyamura, Terue Watanabe
  • Patent number: 10339093
    Abstract: An example system for side band communication can include a processor, a system-on-chip (SOC), and a repeater communicatively coupled to the processor and the SOC. The repeater can receive packets from a first transceiver. The repeater can also detect a pattern in the packets to identify a guest protocol. The repeater can further send the packets from the first transceiver to the SOC via a second transceiver based on the identified guest protocol.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventor: Amit Kumar Srivastava
  • Patent number: 10331600
    Abstract: One or more virtual functions are exposed via a shared communication interface. Memory across said virtual functions is shared to provide a fixed number of I/O buffers shared across said virtual functions. For each of said one or more virtual functions, storing a corresponding map table configured to store a mapping data that maps a logical block address of the virtual function to a corresponding allocated one of said fixed number of I/O buffers based at least in part on a current state of a state machine.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 25, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Samir Rajadnya, Karthik Ramachandran, Todd Wilde
  • Patent number: 10331594
    Abstract: A data transmission method and an electronic apparatus are disclosed. The data transmission method comprises: establishing transmission channels between the local endpoints and a plurality of remote endpoints, wherein at least one of the local endpoints corresponds to at least two of the remote endpoints and at least two transmission channels are established; and transmitting data by using the transmission channels in a time-slice manner between the local endpoints and the corresponding remote endpoints. The data transmission method and the electronic apparatus of the present disclosure can achieve data transmission between a USB host and a plurality of USB devices even when the number of remote endpoints included in the USB devices is greater than the number of local endpoints included in the USB host.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: June 25, 2019
    Assignee: AUTOCHIPS INC.
    Inventor: Zhanyong Wang
  • Patent number: 10324872
    Abstract: Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: June 18, 2019
    Assignee: Intel IP Corporation
    Inventors: Xiang Zou, Hong Wang, Gautham N. Chinya, Perry H. Wang
  • Patent number: 10315087
    Abstract: A method is provided to operate a computer to interoperate with a portable media player. The method includes processing signals provided from the portable media player to the computer that are indicative of whether an accessory has been connected to the portable media player, to determine whether the accessory has been connected to the portable media player. Based on a determination that the accessory has been connected to the portable media player, physiologic data of a user that was provided to the portable media player from a wireless physiologic data gathering device, is received from the portable media player, into the computer, via the accessory.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: June 11, 2019
    Assignee: Apple Inc.
    Inventors: Christopher R. Wysocki, David Heller, Amandeep Jawa, Sandeep Gupta, Greg Marriott, Max Sprauer, David A. Shayer, John Wesley Archibald, Shannon E. Wells
  • Patent number: 10318466
    Abstract: A method and apparatus for handling outstanding interconnect transactions between a master device and an interconnect component. For example, a transaction intervention module coupled to an interconnect component and a master device of the interconnect component. The transaction intervention module is arranged to receive an indication of a functional state of the master device. If the master device is indicated as being in a faulty functional state the transaction intervention module is further arranged to determine whether any interconnect transactions initiated by the master device with the interconnect component are outstanding. If it is determined that at least one interconnect transaction initiated by the master device is outstanding, the transaction intervention module is arranged to finalize the at least one outstanding interconnect transaction with the interconnect component.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Robert Krutsch, Christian Tuschen
  • Patent number: 10318450
    Abstract: Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to define a caching and processing priority policy for one or more input/output (I/O) request class types. The memory controller can monitor one or more I/O contexts of one or more I/O requests. The memory controller can associate the one or more I/O contexts with one or more I/O class types using an I/O context association table. The memory controller can execute the one or more I/O requests according to the caching and processing priority policy of the one or more I/O class types. The apparatus can include an interface to the memory controller.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Maciej Kaminski, Piotr Wysocki, Mariusz Barczak
  • Patent number: 10303647
    Abstract: Computing apparatus includes a central processing unit (CPU), which is configured to run concurrently multiple virtual machines, including at least first and second virtual machines. A peripheral component bus is connected to communicate with the CPU. Multiple peripheral devices are connected to communicate via the bus with the CPU and with others of the peripheral devices, including at least first and second peripheral devices that are each respectively partitioned into at least first and second functional entities, which are respectively assigned to serve the at least first and second virtual machines. Access control logic is configured to forward peer-to-peer communications initiated by the functional entities between the peripheral devices over the bus while inhibiting access in the peer-to-peer communications between the functional entities that are assigned to different ones of the virtual machines.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: May 28, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Adi Menachem, Shachar Raindel
  • Patent number: 10303634
    Abstract: An electronic device includes a connector constituted by plural types of pins and configured to perform a communication in accordance with at least one of a first communication standard for requesting a symmetrical pin arrangement and a second communication standard for requesting an asymmetrical pin arrangement, an input unit configured to input a signal for detecting that an external apparatus connected to the connector is an apparatus in conformity to the first communication standard or the second communication standard via at least one of the pins in the connector, and a control unit configured to perform control in a manner that signal assignment of the plural types of the pins of the connector is switched to a first state corresponding to the first communication standard or a second state corresponding to the second communication standard in accordance with the signal input by the input unit.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 28, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ayumu Nemoto
  • Patent number: 10296228
    Abstract: A storage enclosure includes a plurality of hard drive sub-boards, each configured to include a plurality of hard drives. Each hard drive sub-board is coupled to one or more expanders, via and interface unit, with a set of dual-pass shielded cables. The expander includes a plurality of chipsets coupled to a complex logic device. Each chipset may communicate with a different subset of hard drives with potentially different timing characteristics. The dual-pass shielded cables may be arranged to mitigate these differences. In addition, pin assignments associated with the cables may be set in order to further mitigate the timing differences.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 21, 2019
    Assignee: SUPER MICRO COMPUTER, INC.
    Inventors: Kelvin Tseng, Trina Shih, Lawrence H. Liang, Richard Chen
  • Patent number: 10296263
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device receives a store data object request and facilitates distributed storage of the data object in storage units (SUs). the computing device applies unique deterministic functions to the object name to generate deterministic values. For a deterministic value, the computing device identifies a corresponding SU based on the deterministic value and the bucket mapping scheme. The computing device transmits an update bucket request to the corresponding SU to be used by the corresponding SU to update a state value of a bucket that is locally stored by the corresponding SU to indicate an active state.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Greg R. Dhuse, Jason K. Resch
  • Patent number: 10296246
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 21, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz