Patents Examined by Farley Abad
  • Patent number: 11570489
    Abstract: An HDMI transmission device includes a packetizer circuit and a processor. A control method of controlling the HDMI transmission device includes performing a fixed rate link training, upon passing the fixed data rate link training, the processor transmitting an initial gap packet generation command to a controller of the packetizer circuit to output a selection signal to the packetizer circuit, so as to output an initial gap packet, when video data is not ready, continuously outputting the initial gap packet, when the video data is ready and a format change of the video data is detected or a signal abnormality unrelated to hot-plugging is detected, the processor transmitting a subsequent gap packet generation command to the controller to determine whether a block boundary is reached, and the controller switching the selection signal upon reaching the block boundary for the packetizer circuit to output the subsequent gap packet.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: January 31, 2023
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chun-Chieh Chan, Tai-Jung Wu, Chia-Hao Chang
  • Patent number: 11561883
    Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: January 24, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Masakazu Ehama, Hiroyuki Mizukoshi, Yan Li
  • Patent number: 11556337
    Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: January 17, 2023
    Assignee: Analog Devices International Unlimited Company
    Inventors: Praveen Chandrasekaran, Vinoth Kumar Rajasekar, Shreeja Sugathan
  • Patent number: 11556344
    Abstract: Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O deviceā€”e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator function) can request data from the local HA without these requests having to be sent to the host HA. Further, the accelerator function can indicate whether the local HA tracks the data on a cacheline-basis or by a data block (e.g., multiple cachelines). This provides flexibility that can reduce overhead from tracking the data, depending on the function's desired use of the data.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: January 17, 2023
    Assignee: XILINX, INC.
    Inventors: Millind Mittal, Jaideep Dastidar
  • Patent number: 11550750
    Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 10, 2023
    Assignee: Coherent Logix, Incorporated
    Inventors: Carl S. Dobbs, Keith M. Bindloss, Kenneth R. Faulkner, Alex E. Icaza, Frederick A. Rush, Faisal A. Syed, Michael R. Trocino
  • Patent number: 11550587
    Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: January 10, 2023
    Assignee: C-SKY Microsystems Co., Ltd.
    Inventors: Chen Chen, Dongqi Liu, Tao Jiang, Chaojun Zhao
  • Patent number: 11544526
    Abstract: A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.
    Type: Grant
    Filed: November 28, 2019
    Date of Patent: January 3, 2023
    Inventors: Zidong Du, Shaoli Liu, Tianshi Chen
  • Patent number: 11537865
    Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: December 27, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Krishnakumar Narayanan Nair, Rakesh Komuravelli, Abdulkadir Utku Diril, Ehsan Khish Ardestani Zadeh, Yuchen Hao, Martin Schatz, Thomas Mark Ulrich, Olivia Wu, Anup Ramesh Kadkol, Amin Firoozshahian
  • Patent number: 11531870
    Abstract: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: December 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungho Kim, Cheheung Kim, Jaeho Lee
  • Patent number: 11531635
    Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: December 20, 2022
    Assignee: Intel Corporation
    Inventors: Susanne M. Balle, Evan Custodio, Francesc Guim Bernat, Sujoy Sen, Slawomir Putyrski, Paul Dormitzer, Joseph Grecco
  • Patent number: 11501134
    Abstract: Disclosed is a convolution operator system for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to a set of computing blocks based on the size of the image data and number of available computing blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 15, 2022
    Inventors: Prasanna Venkatesh Balasubramaniyan, Sainarayanan Gopalakrishnan, Gunamani Rajagopal
  • Patent number: 11494609
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for a neural network that is configured to receive a network input and to generate a network output for the network input. The neural network comprises a plurality of layers arranged in a sequence, including a plurality of capsule layers. Each particular capsule in a particular capsule layer is configured to receive respective inputs including: (i) outputs generated by capsules of a previous capsule layer that is before the particular capsule layer in the sequence, and (ii) final routing factors between capsules of the previous capsule layer and the particular capsule, wherein the final routing factors are generated by a routing subsystem. Each particular capsule in the particular capsule layer is configured to determine a particular capsule output based on the received inputs, wherein the particular capsule output is of dimension greater than one.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: November 8, 2022
    Assignee: Google LLC
    Inventors: Geoffrey E. Hinton, Nicholas Myles Wisener Frosst, Sara Sabour Rouh Aghdam
  • Patent number: 11483010
    Abstract: An output control circuit, a method for transmitting data, and an electronic device are disclosed. The output control circuit includes: a serial-to-parallel conversion circuit configured to obtain at least one group of parallel data through a serial-to-parallel conversion; an intermediate-stage cache circuit configured to divide the at least one group of parallel data into at least two categories of subgroup parallel data according to sequence of serial-to-parallel conversion; a latch output circuit including a plurality of latch arrays each of which receiving any category of subgroup parallel data and latching and outputting any subgroup parallel data in any category of subgroup parallel data; and a selection control circuit configured to, within an effective pulse duration of the any subgroup parallel data, control a latch array for the any subgroup parallel data in the plurality of latch arrays to latch and output the any subgroup parallel data.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: October 25, 2022
    Inventors: Junrui Zhang, Xuehui Zhu, Ronghua Lan, Xin Xiang, Xiaoqiao Liu, Xizhu Peng, He Tang
  • Patent number: 11461100
    Abstract: Process address space identifier virtualization uses hardware paging hint.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Kun Tian, Sanjay Kumar, Ashok Raj, Yi Liu, Rajesh M. Sankaran, Philip R. Lantz
  • Patent number: 11449347
    Abstract: Time-multiplexing implementation of hardware accelerated functions includes associating each function of a plurality of functions from program code with an accelerator binary image specifying a hardware accelerated version of the associated function and determining which accelerator binary images are data independent. Using the computer hardware, the accelerator binary images can be scheduled for implementation in a programmable integrated circuit within each of a plurality of partial reconfiguration regions based on data independence.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 20, 2022
    Inventors: Raymond Kong, Brian S. Martin, Hao Yu, Jun Liu, Ashish Sirasao
  • Patent number: 11442729
    Abstract: A method and system for processing a bit-packed array using one or more processors, including determining a data element size of the bit-packed array, determining a lane configuration of a single-instruction multiple-data (SIMD) unit for processing the bit-packed array based at least in part on the determined data element size, the lane configuration being determined from among a plurality of candidate lane configurations, each candidate lane configuration having a different number of vector register lanes and a corresponding bit capacity per vector register lane, configuring the SIMD unit according to the determined lane configuration, and loading one or more data elements into each vector register lane of the SIMD unit. SIMD instructions may be executed on the loaded one or more data elements of each vector register lane in parallel, and a result of the SIMD instruction may be stored in memory.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: September 13, 2022
    Assignee: Google LLC
    Inventors: Junwhan Ahn, Jichuan Chang, Andrew McCormick, Yuanwei Fang, Yixin Luo
  • Patent number: 11436040
    Abstract: A new approach of systems and methods to support a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes a plurality of slave interrupt handlers associated functional blocks in a chip in a hierarchy. When an exception or error condition occurs in a functional block, a slave interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces that have already been utilized for accessing registers of the functional block to transmit the created interrupt packet to a central interrupt handler through the hierarchy without running dedicated interconnect wires out of the functional block.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: September 6, 2022
    Assignee: Marvell Asia Pte Ltd
    Inventors: Saurabh Shrivastava, Guy T. Hutchison
  • Patent number: 11438093
    Abstract: A host/device interface coupled between a host and a storage device, and including a data interface and a Quality of Service (QoS) and configured to communicate a QoS signal with the host. The QoS interface cooperates with the data interface to selectively manage a storage QoS on the storage device. A method is provided for storing data on a data medium including receiving a Quality of Service (QoS) command; selecting a portion of the data medium on which to store a data stream; forming a stream chunk from a portion of the data stream; configuring a transducer to store the stream chunk on the data medium in response to the QoS command; and storing the data on the data medium, such that the storing conforms to a QoS command value.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 6, 2022
    Inventors: Rod Brittner, Ron Benson
  • Patent number: 11429388
    Abstract: Aspects of the current subject matter are directed to an approach in which a parallel load operation of file ID mapping containers is accomplished at start and/or restart of a database system. Parallel load operation of file ID mapping and/or large binary object (LOB) file ID mapping is done among a plurality of scanning engines into a plurality of data buffers that are associated with each of the plurality of scanning engines. Each scanning engine operates on a certain path of a page chain of a page structure including the mapping, causing the page chain to be split among scanning engines to process maps. Contents of the data buffers are pushed to mapping engines via a queue. The mapping engines load the file ID mapping and the LOB file ID mapping into maps for in-system access.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 30, 2022
    Assignee: SAP SE
    Inventors: Dirk Thomsen, Thorsten Glebe, Tobias Scheuer, Werner Thesing, Johannes Gloeckle
  • Patent number: 11422813
    Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of the data register. When the data register includes a boundary-lock pattern or a special symbol, the boundary detector outputs a starting address that the boundary-lock pattern or the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 23, 2022
    Assignee: SILICON MOTION, INC.
    Inventor: Han-Cheng Huang