Abstract: Architectures and techniques to manage resources in a wireless access point. A first set of weights is associated with connected wireless client devices. The first set of weights includes at least one weight for each of the connected wireless client devices. Space is allocated within the packet monitoring buffer to capture packet information for the connected wireless devices using the first set of weights. An indication of an event of interest is received. A second set of weights is associated with the connected wireless client devices. The second set of weights includes at least one weight for each of the connected wireless client devices in response to the indication of the event. Space is allocated within the packet monitoring buffer to capture packet information for the connected wireless devices using the second set of weights.

Abstract: A compute unit includes single-instruction-multiple-data (SIMD) lanes that implement a pipeline. The compute unit also includes a scheduler to schedule the SIMD lanes to apply a binary associative operation to pairs of elements associated with ordered sets of elements. Subsets of the SIMD lanes concurrently apply the binary associative operation to pairs of elements at different levels of upsweep trees associated with the ordered sets of elements. Application of the binary associative operation is used to perform a reduction operation or a scan operation on the ordered sets of elements. In the case of a scan operation, the scheduler schedules the SIMD lanes to concurrently apply the binary associative operation to pairs of elements at different levels of downsweep trees associated with the ordered sets of elements subsequent to applying the binary associative operation at different levels of the upsweep trees.

Abstract: Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or “HCA” for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.

Abstract: An information processing device includes a first processor core of 2n-bits unit, a second processor core of n-bit(s) unit, a DRAM set including a first DRAM and a second DRAM of n-bit(s) unit, a first transmitting path between the first processor core and the DRAM set, a second transmitting path between the second processor core and the first or second DRAM, a transmitting path switching circuit, and a power supply controlling circuit. In normal operation, with switching to the first transmitting path and supplying power to the first processor core and the first and second DRAMs, the first processor core uses the first and second DRAMs. In power saving operation, with switching to the second transmitting path, supplying power to the second processor core and the first DRAM and stopping power to the first processor core and the second DRAM, the second processor core uses the first DRAM.

Abstract: An example method of operating a network may include determining whether a flow is to be added to the network based on: a flow type of the flow, a link condition of the flow, and for each possible combination of flow type and link condition out of multiple flow types and multiple link conditions, the number of flows currently carried on the network that correspond to the respective combination.

Abstract: A system and method for providing system data during a power-on routine of a basic input output system. A controller is powered with an independent power source and accesses the system data. A power-on self-test routine is performed via a basic input output system. The fastest available interface of a plurality of interfaces between the basic input output system and the controller is determined. One of the plurality of interfaces is selected. The system data is sent from the controller to the basic input output system via the selected interface during the power-on self-test routine.

Abstract: Embodiments of the present disclosure are directed toward identifying an indication of a timeout related to a mobile broadband interface model (MBIM) process. The disclosure may also be directed to transmitting, based on the indication of the timeout, an indication of an abort command, wherein the abort command is to provide direction to abort the MBIM process. Other embodiments may be described and/or claimed.

Abstract: A hot-pluggable barrel jack connection system includes a male barrel jack connector including a tip connector at a distal end of the male barrel jack connector and configured to conduct a ground reference voltage, a first ring connector electrically isolated from the tip connector by a first insulator, and configured to conduct a first data signal, and a sleeve connector adjacent to a base of the male barrel jack connector electrically isolated from the first ring connector, and configured to conduct a power signal.

Abstract: Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a first vector and a second vector, wherein the first vector includes one or more first elements and the second vector includes one or more second elements. The aspects may further include one or more adders and a combiner. The one or more adders may be configured to respectively add each of the first elements to a corresponding one of the second elements to generate one or more addition results. The combiner may be configured to combine a combiner configured to combine the one or more addition results into an output vector.

Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.

Abstract: A memory system includes a first nonvolatile memory, a first bridge circuit connected to the memory, a second nonvolatile memory, a second bridge circuit connected to the second memory and connected to the first circuit, and a controller connected to the first circuit and configured to output, to the first circuit, first data to be stored in the first memory and second data to be stored in the second memory, the first and second data being mapped to multiplexing symbols. The first bridge circuit is configured to, upon receipt of the multiplexing symbols, extract the first data from the symbols, store the first data in the first memory, generate third data based on the second data to insert the generated third data into the multiplexing symbols where the first data was mapped, and output to the second circuit the multiplexing symbols into which the third data has been inserted.

Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, the register file having a plurality of entries for storing data and sliced into a plurality of register banks, each register bank having a portion of the plurality of entries for storing data, one or more write ports to write data to the register file entries, and a plurality of read ports to read data from the register file entries; one or more read multiplexors associated with one or more read ports of each register bank and configured to receive data from the respective register banks; and one or more write multiplexors associated with one or more of the register banks.

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

Abstract: Processing circuitry (8) processes software processes at one of a plurality of exception levels and in one of a plurality of realms, each realm corresponding to a portion of at least one software process and being associated with a boundary exception level indicating a most privileged exception level at which the realm can be processed by the processing circuitry (8). In response to a realm exiting exception condition during processing of a given realm, where the exception condition is to be handled by an exception handler at a more privileged exception level than the boundary exception level of the given realm, the processing circuitry (8) performs state masking to make inaccessible, to software processes processed at a more privileged exception level than the boundary exception level, architectural state of a subset of registers selected depending on the boundary exception level of the given realm.

Abstract: Devices, systems and methods for controlling electrical loads in one or more areas. A method includes transmitting, with a microcontroller via a transceiver, a sync packet including a unique address of the lighting fixture control module to a bus. The method includes listening, via the transceiver, on the bus. The method includes placing the microcontroller into a master operation mode when a master sync timeout period expires without receiving a second sync packet including a unique address for a second master device from the bus. The method includes placing the microcontroller into a subordinate operation mode when the second sync packet is received from the bus during the master sync timeout period.

Abstract: A seemingly monolithic interface between separate integrated circuit die may appear to be parallel or asynchronous from the perspective of the separate integrated circuit die. The signals of the seemingly monolithic interface, however, may actually be communicated between the separate die via serial and/or synchronous communication. In one method, a number of signals stored in a first parallel interface on a first integrated circuit die may be sampled. In some cases, at least one of the signals may be sampled more often than another one of the signals. A serial signal may be generated based on sampled signals. The serial signal may be transmitted to a corresponding second parallel interface on the second integrated circuit die.

Abstract: A method in a multiprocessor system for processing multiple perception streams is disclosed. The method comprises: reading data from a plurality of perception streams according to a reading schedule determined by a predetermined policy, each perception stream comprising perception data from a different perception sensor; assigning a unique identification tag to each perception stream; writing each perception stream with its unique identification tag to a server input queue based on the predetermined policy; and processing the tagged perception streams using a server. The processing includes: retrieving tagged perception streams from the server input queue; applying a processing algorithm to process the retrieved tagged perception streams; and outputting the processed perception streams to a server output queue.

Abstract: Implementations described herein provide apparatus and methods for storing data in, and retrieving data from, storage buffer having an odd number of storage locations using minimal additional logic. A binary address symbol with a maximum value of one less than twice the number of storage locations is used to allow use of Gray code in transferring the storage location pointers between clock domains. An offset value is added to the binary address symbol to further facilitate use of Gray code. The Gray code is converted back to a binary symbol at the read side, the offset value is subtracted therefrom, and a pointer to a particular storage location is resolved.

Abstract: A system and method for adapting an audios stream for reducing latency. The method may include the steps of, and the system may function to, receive an audio stream having a packet buffer and an audio buffer, measure the audio buffer depth of the audio buffer, measure the presentation time margin of at the input to the packet buffer, and determine an adaptation level for latency based on the measured values.

Abstract: A processing apparatus includes a processor. The processor stores a plurality of instruction codes, each of the plurality of instruction codes is a result of decoding of an instruction, selects an instruction code that is ready to be input from the stored instruction codes, when the selected instruction code is an operation instruction, uses for the processing, a register for processing corresponding to a write destination of the operation instruction, after detecting that operands to be used for the processing are ready, in the next cycle, issues a subsequent instruction, and when the selected instruction code is a memory access instruction, uses for the address calculation, the register, writes a processing result and load data that have been temporarily written in a buffer for register update from the buffer to the register at the time of instruction completion, after the completion of the memory access instruction, issues a subsequent instruction.