Abstract: Embodiments may be generally direct to apparatuses, systems, method, and techniques to detect a message to communicate via an interconnect coupled with a device capable of communication via a plurality of interconnect protocols, the plurality of interconnect protocols comprising a non-coherent interconnect protocol, a coherent interconnect protocol, and a memory interconnect protocol. Embodiments also include determining an interconnect protocol of the plurality of interconnect protocols to communicate the message via the interconnect based on the message, and providing the message to a multi-protocol multiplexer coupled with the interconnect, the multi-protocol multiplexer to communicate the message utilizing the interconnect protocol via the interconnect with the device.

Abstract: Disclosed are methods, systems, and other techniques for modeling concurrency between a set of nodes to be executed on a set of execution engines of an integrated circuit device. A computation graph that includes the set of nodes is received. A set of edges connecting the set of nodes are determined based on the computation graph. An edge type for each of the set of edges is determined based on the computation graph, the edge type indicating a type of synchronization between connected nodes. A vector clock is generated for each of the set of nodes, the vector clock for a particular node being calculated based on the vector clock for each connected preceding node and the edge type for the one of the set of edges that connects each connected preceding node and the particular node.

Abstract: An intra-chassis device multi-management domain system includes a chassis housing a host processing system connected to first device(s), a secondary processing system connected to second device(s), and a management system connected to the first and second device(s). The management system may receive a first request for management access including first management domain access credentials, determine that the first management domain access credentials allow first access to a host domain associated with the host processing system and, in response, provide the first access to the first device(s) connected to the host processing system.

Abstract: A physical quantity detection device that can improve arithmetic resolution while preventing an increase in memory capacity is obtained. A physical quantity detection device 100 according to the present invention includes: a physical quantity detection sensor that detects a physical quantity of a measurement target gas; a storage unit that records a correction amount corresponding to a detection value of the physical quantity detection sensor; and an arithmetic unit 110 that performs output adjustment of the detection value using the detection value and the correction amount. Resolution of the storage unit 120 is lower than arithmetic resolution of the arithmetic unit 110.

Abstract: A hardware decompression acceleration engine including: an input buffer for receiving to-be-decompressed data from a software layer of a host computer; a decompression processing unit coupled to the input buffer for decompressing the to-be-decompressed data, the decompression processing unit further receiving first and second flags from the software layer of the host computer, wherein the first flag is indicative of a location of the to-be-decompressed data in a to-be-decompressed data block and the second flag is indicative of a presence of an intermediate state; and an output buffer for storing decompressed data from the decompression processing unit.

Abstract: Embodiments of systems and methods for managing an Information Handling System (IHS) using a workspace orchestration system are described. In an illustrative, non-limiting embodiment, an IHS may include computer-executable instructions to, instantiate a first workspace comprising a cache database, the first workspace being instantiated with a first interface that is configured to communicate with a second interface configured in a second workspace administered by the workspace orchestration system. The cache database being accessed by the second workspace using the first interface.

Abstract: A display control method for a peripheral device shared by a plurality of user terminals includes: storing a connection history of a user terminal for connecting the peripheral device; storing settings information specifying an operation of the peripheral device, the settings information being associated with identification information of the user terminal; selecting settings information stored in the storing settings information or identification information of a user terminal on the basis of the connection history stored in the storing a connection history; and displaying settings information or identification information selected in the selecting.

Abstract: Transmitter circuitry includes inversion circuitry, first transform circuitry, and selection circuitry. The inversion circuitry generates a first transformed data word by inverting one or more of a plurality of bits of a first data word. The first transform circuitry generates a second transformed data word by performing a first invertible operation on the first data word and a second data word. The selection circuitry selects one of the first data word, the first transformed data word, and the second transformed data word based on a first number of bit inversions between the first data word and the second data word, a second number of bit inversions between the first transformed data word and the second data word, and a third number of bit inversions between the second transformed data word and the second data word. The selection circuitry further outputs the selected data word.

Abstract: A system and method for efficiently arbitrating traffic on a bus. A computing system includes a fabric for routing traffic among one or more agents and one or more endpoints. The fabric includes multiple arbiters in an arbitration hierarchy. Arbiters store traffic in buffers with each buffer associated with a particular traffic type and a source of the traffic. Arbiters maintain a respective urgency counter for keeping track of a period of time traffic of a particular type is blocked by upstream arbiters. When the block is removed, the traffic of the particular type has priority for selection based on the urgency counter. When arbiters receive feedback from downstream arbiters or sources, the arbiters adjust selection priority accordingly. For example, changes in bandwidth requirement, low latency tolerance and active status cause adjustments in selection priority of stored requests.

Abstract: Running an independent task in connection with a synchronous I/O operation between a storage system and a host includes starting the synchronous I/O operation, setting a timer for the synchronous I/O operation, starting the independent task that runs while waiting for completion of the synchronous I/O operation, and aborting the synchronous I/O operation in response to the timer expiring prior to completion of the synchronous I/O operation. The independent task may be ended in response to the timer expiring. The independent task may be ended in response to the I/O operation completing. The synchronous I/O operation may be performed using a high speed connection between the storage system and the host, which may be coupled to a smart network interface controller provided on a director board in the storage system. The smart network interface controller may include a system on a chip having a processor, memory, and non-volatile storage.

Abstract: Extending fused multiply-add instructions, including: receiving an extended fused multiply-add (FMA) instruction comprising a first subset of bits indicating a corresponding register for each operand of a fused multiply-add (FMA) operation and a second subset of bits indicating a different register storing data describing one or more transformations applicable to one or more operands of the FMA operation; and performing, based on the extended FMA instruction.

Abstract: Embodiments are directed to selecting a multiplication operation to be scheduled in a first stage of an execution schedule, the multiplication operation meeting a first condition of having no dependency. An addition/subtraction operation is selected to be scheduled in the first stage of the execution schedule responsive to meeting the first condition. A process is performed which includes selecting another multiplication operation to be scheduled in a next stage of the execution schedule responsive to meeting the first condition or a second condition, the second condition including having a dependency that is fulfilled by a previous stage. The process includes selecting another addition/subtraction operation to be scheduled in the next stage of the execution schedule responsive to meeting the first or second condition, and repeating the process until each operation has been scheduled in the execution schedule, where the execution schedule is configured for execution by an arithmetic logic unit.

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Abstract: A computing device includes a transport switch comprising read and write switches that provide switched circuit interconnections between input and output ports for simultaneous data communication between a plurality of memory clients and a plurality of memory banks, such as between cores of a multi-core processor simultaneously accessing L1, L2, and L3 memory banks. Embodiments implement switching designs that are derived from existing switched network architectures. Other embodiments implement a novel circuit switch design based on 8×8 building blocks. The transport switch can be non-blocking, and can be self-routing. An additional switching layer can be included to provide port rearrangement for rearrangeable non-blocking switches. A transport compiler can be used to determine port-pair configurations of the switch. A disclosed method selects optimal switch architectures for specific applications.

Abstract: An integrated circuit (IC) includes a first circuit including a timer for receiving an adjustable clock signal. Responsive to leaving the non-operational power state to enter a power state in which the adjustable clock has a lower frequency than the reference clock, the first circuit adjusts the frequency of the adjustable clock to a frequency higher than the lower frequency, and then receives an elapsed time associated with the non-operational power state and starts the timer using an adjusted timer value.

Abstract: A system including a sensor interface for determining a substitute frequency value via a sensor interface is provided. The system can include a first circuit receiving a frequency signal. The system can also include a sensor interface coupled to the first circuit and configured to determine a substitute frequency value based on the frequency signal. The system can also include a second circuit providing the substitute frequency value output from the sensor interface. The second circuit can provide the substitute frequency value in place of an analog input value by mimicking the behavior of an analog-to-digital converter. An apparatus including the sensor interface and methods of determining the substitute frequency value using a sensor interface are also provided.

Abstract: A bus interconnection system and a method for detecting bad routing by the same are provided. The bus interconnection system includes a master node, destination nodes, and a first order switch node. The destination nodes include slave nodes, the bus interconnection system assigns an identification symbol to each of the destination nodes, and adds a destination identification symbol to data sent to the slave nodes by the master node through the first order switch node. When the first order switch node receives the data, the first order switch node updates the destination identification symbol of the data according to a payload of the data, and when one of the destination nodes receives the data, the one of the destination nodes determines whether a bad routing occurs by checking whether the destination identification symbol is equal to the identification symbol assigned to the destination node that receives the data.

Abstract: A process control input/output (I/O) device provides traditional I/O support with direct physical layers or interfaces associated with traditional process control communication protocols while at the same time supporting an advanced physical layer or other IP based physical layer and the communication protocols that run on top of them. In addition, the new I/O device is able to nest protocols inside of other protocols for use when protocols, such as safety protocols, require additional handshaking, confirmations, etc. Still further, the new I/O device includes hardware configurable capabilities that enable easy configuration of a process control system that uses multiple different physical layers, including those used by traditional process control protocols such as HART and FOUNDATION Fieldbus protocols, and more advanced physical layers, including those that are used by IP-based, Ethernet based, packet based and other types of advanced communication protocols.

Abstract: According to one general aspect, a non-transitory computer readable medium includes instructions that, when executed by at least one processor, cause a computing device to read a string of a log file for an application, where the log file comprises multiple strings of log data, compare the string to signatures stored in a memory to find a matching signature, where each of the signatures is encoded with a signature identifier (ID), determine a deviation between the string and the matching signature, encode the string with the signature identifier (ID) of the matching signature and the deviation, and transfer the string to a destination computing device using the signature identifier (ID) of the matching signature, the deviation, and a timestamp of the string.

Abstract: Systems or methods of the present disclosure may provide high-bandwidth, low-latency connectivity for inter-die and/or intra-die communication of a modularized integrated circuit system. Such an integrated circuit system may include a first die of fabric circuitry sector(s), a second die of modular periphery intellectual property (IP), a passive silicon interposer coupling the first die to the second die, and a modular interface that includes a network-on-chip (NOC). The modular interface may provide high-bandwidth, low-latency communication between the first die and the second, between the fabric circuitry sector(s), and between the first die and a third die.