Abstract: Various implementations described herein relate to systems and methods for a solid state drive (SSD) that includes a first controller and a NAND package. The NAND package includes a plurality of dies grouped into a plurality of subsets. The NAND package includes a second controller operatively coupled to each of the plurality of subsets via a corresponding one of a plurality of parallel mode channels. The first controller is operatively coupled to the NAND package via a serial link.

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

Abstract: Techniques and apparatus for dynamically modifying a kernel (and associated user-specified circuitry) for a dynamic region of a programmable integrated circuit (IC) without affecting (e.g., while allowing) operation of other kernels ((and other associated user-specified circuitry) in the programmable IC. Dynamically modifying a kernel may include, for example, unloading an existing kernel, loading a new kernel, or replacing a first kernel with a second kernel). In the case of networking (e.g., in a data center application) where the programmable IC may be part of a hardware acceleration card (e.g., a network interface card (NIC)), the kernel may be user code referred to as a “plugin.

Abstract: Techniques are provided to implement hardware accelerated application of preconditioners to solve linear equations. For example, a system includes a processor, and a resistive processing unit coupled to the processor. The resistive processing unit includes an array of cells which include respective resistive devices, wherein at least a portion of the resistive devices are tunable to encode entries of a preconditioning matrix which is storable in the array of cells. When the preconditioning matrix is stored in the array of cells, the processor is configured to apply the preconditioning matrix to a plurality of residual vectors by executing a process which includes performing analog matrix-vector multiplication operations on the preconditioning matrix and respective ones of the plurality of residual vectors to generate a plurality of output vectors used in one or more subsequent operations.

Abstract: A computer interlocking system includes: a first sub-system and a second sub-system that have a same structure and function, where the first sub-system and the second sub-system form a double 2-vote-2 architecture, respectively including a main control layer, a network layer, and a communication and execution layer; the network layer being configured to construct a communication network of a sub-system in which the network layer is located; the main control layer and the communication and execution layer in the first sub-system being respectively connected to a communication network of the first sub-system; and the main control layer and the communication and execution layer in the second sub-system being respectively connected to a communication network of the second sub-system.

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

Abstract: The present disclosure provides a systolic array-based data processing method that includes determining an input splice quantity for the systolic array based on a target input depth and a standard input depth, and determining an output splice quantity for the systolic array based on a target output depth and a standard output depth; inputting the input data matching the input splice quantity to an input buffer of the systolic array in batches, without overlaps in the input data, and processing, by the systolic array, the input data in the input buffer to generate output data corresponding to each piece of input data; and in accordance with a determination that a quantity of output data received by an output buffer of the systolic array from the systolic array matches the output splice quantity, outputting, in the output buffer, output data having a quantity matching the output splice quantity in batches.

Abstract: The example embodiments provide a method, a system, a mobile device, and an acceleration device for processing computing jobs. The method includes: obtaining, by a mobile device, a computing job, wherein a first interface of the mobile device is connected to a second interface, the second interface included in an acceleration device; transmitting, by the mobile device, the computing job from the first interface to the second interface via a write command; receiving, by the acceleration device, the computing job at the second interface; processing, by the acceleration device, the computing job and transmitting a processing result from the second interface to the first interface; and obtaining, by the mobile device, the processing result from the first interface via a read command.

Abstract: A processing in memory (PIM) device includes a memory configured to receive data through a first path from a host processor provided outside the PIM device, and an information gatherer configured to receive the data through a second path connected to the first path when the data is transferred to the memory via the first path, and to generate information by processing the data received through the second path.

Abstract: This document describes techniques and apparatuses that enable determining expected hash-values in functions with control flow. A computing device receives a function comprising function instructions within at least three basic blocks connected via multiple execution paths. Hash-input instructions are inserted within a plurality of the basic blocks that indirectly force hash values at the respective insertion points. Hash values at ends of the plurality of the basic blocks are set to a canonical value and an expected hash-value and hash input-values are calculated using a hash function. By using the canonical value and the hash input-values, the expected hash-value is the same regardless of which execution path is executed.

Abstract: A system for processing a plurality of concurrent threads comprising: a reconfigurable processing grid, comprising logical elements and a context storage for storing thread contexts, each thread context for one of a plurality of concurrent threads, each implementing a dataflow graph comprising an identified operation; and a hardware processor configured for configuring the at reconfigurable processing grid for: executing a first thread of the plurality of concurrent threads; and while executing the first thread: storing a runtime context value of the first thread in the context storage; while waiting for completion of the identified operation by identified logical elements, executing the identified operation of a second thread by the identified logical element; and when execution of the identified operation of the first thread completes: retrieving the runtime context value of the first thread from the context storage; and executing another operation of the first thread.

Abstract: A topology is disclosed. The topology may include at least one Non-Volatile Memory Express (NVMe) Solid State Drive (SSD), a Field Programmable Gate Array (FPGA) to implement one or more functions supporting the NVMe SSD, such as data acceleration, data deduplication, data integrity, data encryption, and data compression, and a Peripheral Component Interconnect Express (PCIe) switch. The PCIe switch may communicate with both the FPGA and the NVMe SSD.

Abstract: An embodiment of the present invention relates to physical interfaces, especially those used on consumer electronics devices. A processor, in which an embodiment of the disclosed invention is deployed, includes a physical interface for connecting to and communicating with a peripheral device, the peripheral device being configured to operate according to a standard communications protocol or to a different protocol which is adapted to have a more bandwidth-efficient performance. The processor detects which of the two protocols the attached peripheral device uses and configures the physical interface to operate according to the detected protocol. An embodiment of the invention allows for new, bandwidth-efficient communications protocols to be executed across existing standardized physical interface hardware, thereby allowing for easier acceptance of the new protocols within the consumer electronics industry.

Abstract: Disclosed are an inter-core data processing method and system, a system on chip, and an electronic device. The method includes: a first core sends, by means of a command transmission module, to a second core a first command indicating that the first core is ready to perform a data processing operation corresponding to a target address; the second core acquires a mutex corresponding to the target address in response to the first command and returns a second command to the first core by means of the command transmission module; and the first core performs the data processing operation corresponding to the target address by means of a bus module in response to the second command.

Abstract: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.

Abstract: A processing-in-memory (PIM) device includes a data selection circuit, a multiplying-and-accumulating (MAC) circuit, and an accumulative adding circuit. The data selection circuit generates selection data from input data and zero-point data based on a zero-point selection signal. The MAC circuit performs a MAC arithmetic operation for the selection data to generate MAC result data. The accumulative adding circuit accumulatively adds MAC sign data based on a MAC output latch signal to generate MAC latch data. A sign of the MAC sign data is determined by the zero-point selection signal.

Abstract: An apparatus comprises processing circuitry which has a hypervisor execution mode for execution of a hypervisor for managing one or more virtual processors executing on the processing circuitry, and at least one less privileged execution mode than the hypervisor execution mode. In response to a conditional yield to hypervisor instruction executed in the at least one less privileged execution mode, an instruction decoder controls the processing circuitry to determine whether at least one trap condition is satisfied, and when the at least one trap condition is determined to be satisfied, to switch the processing circuitry to the hypervisor execution mode; and store, in at least one storage element accessible to instructions executed in the hypervisor execution mode, at least one item of scheduling hint information for estimating whether the at least one trap condition is still satisfied.

Abstract: Systems, methods, and media for managing an entertainment system are provided. In some implementations, systems for managing an entertainment system are provided, the systems comprising: at least one hardware processor configured to: detect a first instruction; select a component of the entertainment system; determine a first state of the component; store an indication of the first state; detect a second instruction; retrieve the indication of the first state; generate a third instruction based on the indication of the first state; and transmit the third instruction to the component of the entertainment system.

Abstract: A fractal computing device according to an embodiment of the present application may be included in an integrated circuit device. The integrated circuit device includes a universal interconnect interface and other processing devices. The calculating device interacts with other processing devices to jointly complete a user specified calculation operation. The integrated circuit device may also include a storage device. The storage device is respectively connected with the calculating device and other processing devices and is used for data storage of the computing device and other processing devices.

Abstract: A memory array arranged in multiple columns and rows. Computation circuits that each calculate a computation value from cell values in a corresponding column. A column multiplexer cycles through multiple data lines that each corresponds to a computation circuit. Cluster cycle management circuitry determines a number of multiplexer cycles based on a number of columns storing data of a compute cluster. A sensing circuit obtains the computation values from the computation circuits via the column multiplexer as the column multiplexer cycles through the data lines. The sensing circuit combines the obtained computation values over the determined number of multiplexer cycles. A first clock may initiate the multiplexer to cycle through its data lines for the determined number of multiplexer cycles, and a second clock may initiate each individual cycle. The multiplexer or additional circuitry may be utilized to modify the order in which data is written to the columns.