Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Abstract: The present disclosure relates to methods and apparatus for compute processing. For example, disclosed techniques facilitate improving performance of matrix multiplication in streaming processor. Aspects of the present disclosure can execute, with a load control unit, a first load instruction to load a set of input data of an input matrix from a first memory to a second memory. Aspects of the present disclosure can also execute, with the load control unit, a second load instruction to load a set of weight data of a weight matrix from the first memory to the second memory. Additionally, aspects of the present disclosure can perform, with an ALU component, a matrix multiplication operation using the set of input data and the set of weight data to generate an output matrix. Further, aspects of the present disclosure can store the output matrix at a general purpose register accessible to the ALU component.

Abstract: Systems, apparatuses, and methods related to acceleration circuitry for posit operations are described. Signaling indicative of performance of an operation to write a first bit string to a first buffer resident on acceleration circuitry and a second bit string resident on the acceleration circuitry can be received at an DMA controller couplable to the acceleration circuitry. The acceleration circuitry can be configured to perform arithmetic operations, logical operations, or both on bit strings formatted in a unum or posit format. Signaling indicative of an arithmetic operation, a logical operation, or both, to be performed using the first and second bit strings can be transmitted to the acceleration circuitry. The arithmetic operation, the logical operation, or both can be performed via the acceleration circuitry and according to the signaling. Signaling indicative of a result of the arithmetic operation, the logical operation, or both can be transmitting to the DMA controller.

Abstract: The invention introduces an apparatus for segmenting a data stream, installed in a physical layer, to include a host interface, a data register and a boundary detector. The data register is arranged to operably store data received from the host side through the host interface. The boundary detector is arranged to operably detect the content of a data register. When the data register includes a special symbol, the boundary detector outputs a starting address that the special symbol is stored in the data register to an offset register to update a value stored in the offset register, thereby enabling a stream splitter to divide data bits of the data register according to the updated value of the offset register.

Abstract: A computing system includes a processing unit and a network device. The processing unit includes a first baseboard management controller (BMC), an external network interface coupled to the first BMC, and a first internal network interface coupled to the first BMC. The network device includes a second BMC and a second internal network interface coupled to the second BMC. The second internal network interface of the network device is connected to the first internal network interface of the processing unit. The first BMC is configured to transfer data between an external network and the second BMC via (i) the external network interface, (ii) the first internal network interface, and (iii) the second internal network interface.

Abstract: A reconfigurable data acquisition card including at least one field programmable gate array (FPGA) and a configurable bus switch coupled with the FPGA. The bus switch forms at least first and second ports used by the FPGA, the bus switch being adaptable for insertion into a connection having a number of lanes at least equal to a combined number of lanes in the first and second ports. The data acquisition card further includes multiple optical transmitters and optical receivers. Each optical transmitter and optical receiver is coupled with a corresponding transceiver in the FPGA via at least one optical fiber having multiple communication links. Timing circuitry in the data acquisition card is coupled with clock generation and distribution circuitry in the FPGA and is configured to distribute clock and timing signals to detector front-ends with fixed latency and to synchronize input/output links with a system clock generated by the FPGA.

Abstract: A power source circuit includes: a plurality of power supply circuits which are electrically connected to different positions in a power supply wiring through which power is supplied to a plurality of processing circuits, wherein each of the power supply circuits is configured to generate a power supply voltage with reference to an input reference voltage, and supply the power supply voltage to the power supply wiring; and a reference voltage supply circuit generate a plurality of reference voltages with different voltages and to each of the plurality of power supply circuits, supply one of the different reference voltages as the input reference voltage thereof.

Abstract: A method performed by a device connected to a host processor via a bus includes: providing a first read request including a first address to a memory; receiving a second address stored in a first region of the memory corresponding to the first address, from the memory; providing a second read request including the second address to the memory; and receiving first data stored in a second region of the memory corresponding to the second address, from the memory, wherein the first read request further includes information indicating that the first address is an indirect address of the first data.

Abstract: An information handling system includes a secondary baseboard management controller that may transmit a first set of data via an external interface, and transmit a second set of data via an internal interface. A primary baseboard management controller includes a data traffic manager that may transmit a first signal for the current data to be transmitted if the current data is of the first set of data, or transmit a second signal if the current data is of the second set of data.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: The Multicore Bus Architecture (MBA) protocol includes a novel technique of sharing the same physical channel for all transaction types. Two channels, the Transaction Attribute Channel (TAC) and the Transaction Data Channel (TDC) are used. The attribute channel transmits bus transaction attribute information optionally including a transaction type signal, a transaction ID, a valid signal, a bus agent ID signal, an address signal, a transaction size signal, a credit spend signal and a credit return signal. The data channel connected a data subset of the signal lines of the bus separate from the attribute subset of signal lines the bus. The data channel optionally transmits a data valid signal, a transaction ID signal, a bus agent ID signal and a last data signal to mark the last data of a current bus transaction.

Abstract: Various implementations described herein relate to systems and methods for collecting Solid State Drive (SSD) statistics. A controller, in response to receiving a start command from a host, creates a slot area in a storage device of the SSD corresponding to a slot, collects first statistics data from one or more modules of the SSD, and stores the first statistics data in the slot area. Further, the controller, in response to receiving a stop command, collects second statistics data from the one or more modules and sends the first statistics data and the second statistics data to the host.

Abstract: A memory is accessed based on memory access requests that has different data read sizes. A memory access method includes outputting each of read commands corresponding to the plurality of memory access requests to a memory at a timing that avoids conflict of read data output from the memory; generating an output start timing of the data read from the memory to an outside; retaining the data read from the memory in each of buffers, and causing any of the plurality of buffers to output data based on the output start timing; and delaying, in a case of receiving a subsequent memory access request during execution of memory access corresponding to a preceding memory access request, the output start timing of data from the buffer corresponding to the subsequent memory access request from the output start timing of data from the buffer corresponding to the preceding memory access request.

Abstract: An electronic control device includes a processing control unit and an information acquisition unit.

Abstract: Provided is a tensor decomposition processing system capable of comprehensively finding factors obtained by tensor decomposition on a given tensor. A decomposition execution unit 3 executes tensor decomposition on a given tensor a plurality of times until a predetermined end condition is satisfied. A condition determination unit 5 determines whether the predetermined end condition is satisfied. When executing the tensor decomposition on the tensor, the decomposition execution unit 3 executes the tensor decomposition under a constraint of obtaining factors different from factors obtained by previous execution of the tensor decomposition.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Abstract: An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time.

Abstract: Various embodiments of the present technology may provide methods and apparatus for reordering signals that are generated by a sensor. The apparatus may receive the generated signals in the form of a plurality of X-bit input signals and generate a plurality of output signals according to an exemplary reordering scheme. The apparatus may perform the exemplary reordering scheme based on one or more states of a state machine.

Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.