Abstract: Machine templates are described herein that provide for enhanced configuration and deployment of arrangements of physical computing components coupled over a communication fabric. In one example, a method includes presenting a user interface indicating a plurality of templates each specifying at least a predefined arrangement of physical computing components for inclusion in compute units, and receiving a user selection indicating a selected template among the plurality of templates to form a target compute unit. The method includes allocating to the target compute unit a set of physical computing components according to the selected template, and instructing a management entity to establish the target compute unit based at least on logical partitioning within a communication fabric communicatively coupling the set of physical computing components of the target compute unit.

Abstract: A cross-host multi-hypervisor system, including a plurality of host sites, each site including at least one hypervisor, each of which includes at least one virtual server, at least one virtual disk that is read from and written to by the at least one virtual server, a tapping driver in communication with the at least one virtual server, which intercepts write requests made by any one of the at least one virtual server to any one of the at least one virtual disk, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted write requests from the tapping driver, and which provides data services based thereon, and a data services manager for coordinating the virtual data services appliances at the site, and a network for communicatively coupling the plurality of sites, wherein the data services managers coordinate data transfer across the plurality of sites via the network.

Abstract: Many computing systems process data organized in a matrix format. For example, artificial neural networks (ANNs) perform numerous computations on data organized into matrices using conventional matrix arithmetic operations. One such operation, which is commonly performed, is the transpose operation. Additionally, many such systems need to process many matrices and/or matrices that are large in size. For sparse matrices that hold few significant values and many values that can be ignored, transmitting and processing all the values in such matrices is wasteful. Thus, techniques are introduced for storing a sparse matrix in a compressed format that allows for a matrix transpose operation to be performed on the compressed matrix without having to first decompress the compressed matrix. By utilizing the introduced techniques, more matrix operations can be performed than conventional systems.

Abstract: The present invention provides a pin multiplexer including a multiplexing circuit, a control circuit and a detecting circuit. The multiplexing circuit includes a first port, a second port and a third port, wherein the first port, the second port and the third port are coupled to a first device, a second device and a third device, respectively. The control circuit is configured to control the multiplexing circuit to operate in a first mode or a second mode, wherein when the multiplexing circuit operates in the first mode, the first port is coupled the second port; and when the multiplexing circuit operates in the second mode, the first port is coupled to the third port. When operating in the second mode, the detecting circuit detects a signal of the first port to generate a detection result for dynamically switching the data transmission direction between the third device and the first device.

Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a device context device driver for forced detaching of an application from mapped devices. The device context device driver receives a command to detach an application, wherein the command specifies a process descriptor associated with the application. The device context device driver identifies a plurality of matching device context entries in a list of open device contexts maintained by the device context device driver that match the process descriptor. The device context device driver marks the plurality of matching device context entries as detached. The device context device driver invalidates mapped memory areas associated with the plurality of matching device context entries.

Abstract: The invention enables commissioning of field devices within a control system by implementing the steps of (i) detecting a connection event comprising a field device interfacing with an I/O port that is communicably coupled with the server, (ii) retrieving from a memory of the field device that is interfacing with the I/O port, a first field device identifier corresponding to the field device, (iii) retrieving from a non-transient memory database communicably coupled with the server, field device configuration data associated with the I/O port, wherein, the set of field device attributes includes a second field device identifier, and at least a segment of the second field device identifier is different from a corresponding segment of the first field device identifier, (iv) generating one of a translated first field device identifier and a translated second field device identifier, based on predefined translation data, (v) comparing the translated first field device identifier with the second field device ident

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for fetching data for an accelerator. The methods include detecting an attempt to access a first page of data that is not stored on a primary storage unit of the accelerator; and responsive to detecting the attempt to access the first page of data: assessing activity of the accelerator; determining, based on the assessed activity of the accelerator, a prefetch granularity size; and transferring a chunk of contiguous pages of data of the prefetch granularity size from a memory system connected to the accelerator into the primary storage unit, wherein the transferred chunk of contiguous pages of data include the first page of data.

Abstract: Circuitry comprises a prediction register storing a plurality of entries each having respective data values for association with one or more branch instructions; prediction circuitry to detect, using prediction data derived by a mapping function from the stored data values associated with a given branch instruction, whether or not a branch represented by the given branch instruction is predicted to be taken; update circuitry to modify the stored data values associated with the given branch instruction in dependence upon a resolution of whether the branch represented by the given branch instruction is taken or not; and control circuitry configured to selectively alter one or more of the data values other than data values associated with the given branch instruction.

Abstract: According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input/output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.

Abstract: Example implementations relate to SATA and NVMe device determination. An example method can include determining a device type communicatively coupled to an M.2 socket of a central processing unit (CPU) based on a PEDET signal from the M.2 socket. The method can include configuring a crossbar switch to route a plurality of serial AT attachment (SATA) signals to the M.2 socket in response to a determination that the device is a SATA device type. The method can include configuring the crossbar switch and a multiplexer to route a plurality of non-volatile memory express (NVMe) signals to the M.2 socket in response to a determination that the device is an NVMe device type.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: Embodiments of the invention are generally directed to transmission and detection of multi-channel signals in reduced channel format. An embodiment of a method for transmitting data includes determining whether a first type or a second type of content data is to be transmitted, where the first type of content data is to be transmitted at a first multiple of a base frequency and the second type of data is to be transmitted at a second multiple of the base frequency. The method further includes selecting one or more channels from a plurality of channels based on the type of content data, clocking a frequency on the first or second multiple of the base frequency according to the type of content data in the selected channels, modifying the content data to fit within a single output channel, and transmitting the modified data via a single output channel at the chosen multiple of the base frequency.

Abstract: A method, an improvement evaluation system and a computer readable medium are usable for automatically calculating an improvement evaluation result for operating a set of registered applications. Each of the set of registered applications of the system includes a declaration interface, adapted for providing a self-declaration by way of a formula, indicating whether the application is operated under pre-defined success conditions; and a collector, adapted for collecting measurement data during runtime to be introduced in the formula. The system further includes a network for transferring the formula to an evaluation unit for evaluation; and a result interface for providing an improvement evaluation result, reflecting an improvement potential for the respective application to be operated in the set of applications.

Abstract: Apparatuses, methods, programs, and complex number processing instructions are provided to support vector processing operations on input data vectors comprising a plurality of input data items at respective positions in the input data vectors. In response to the instructions at least one first set of data items is extracted from alternating positions in a first source register and at least one second set of data items is extracted from alternating positions in the second source register, wherein consecutive data items in the first and second source registers comprise alternating real and imaginary components of respective sets of complex numbers. A result set of complex number components is generated using the two sets of data items as operands, and the result set of complex number components is one of a real part and an imaginary part of a complex number result of the complex number operation applied to the two sets of complex numbers.

Abstract: Example object storage systems, bookkeeping engines, and methods provide quota-based access control for control entities, such as accounts, users, and buckets. An object data store is configured to enable control entities to access data objects associated with each control entity. Quota thresholds and usage values are determined for control entities and used to determine a quota status. Quota status is used to determine data object access response based on the requesting control entities.

Abstract: A microprocessor using a counter in a scoreboard is introduced to handle data dependency. The microprocessor includes a register file having a plurality of registers mapped to entries of the scoreboard. Each entry of the scoreboard has a counter that tracks the data dependency of each of the registers. The counter decrements for every clock cycle until the counter resets itself when it counts down to 0. With the implementation of the counter in the scoreboard, the instruction pipeline may be managed according to the number of clock cycles of a previous issued instruction takes to access the register which is recorded in the counter of the scoreboard.

Abstract: An apparatus comprises a processing device comprising a processor coupled to memory. The processing device is configured to obtain maintenance information comprising an indication that a port of a storage system is scheduled for a maintenance activity and to determine that a host device utilizes the port for communication with the storage system. The processing device is further configured to issue an alert to the host device. The alert is configured to cause the host device to set a path associated with the port to a standby mode. The standby mode is configured to inhibit input-output operations from being submitted to the storage system along the path.

Abstract: According to one embodiment, an electronic apparatus includes a connection unit configured to be capable of being connected to a host device, a storage unit configured to store device classes of a plurality of types, a processing unit configured to execute processing for establishing communication with the host device connected to the connection unit by selectively using one device class from among the device classes stored in the storage unit, and a processing control unit configured to change the device class to be used for the processing by the processing unit if a message appropriate for the selected device class is not transmitted from the host device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.