Abstract: A complex programmable logic device includes a SGPIO analyzing circuit, a I2C analyzing circuit and a first multiplexer. The SGPIO analyzing circuit has a plurality of port analyzing circuits, a detecting circuit and a processing circuit. Each port analyzing circuit receives an input signal and outputs a first data. The detecting circuit detects the input signal of the first port analyzing circuit to output a detecting signal. The processing circuit captures port information of the first data outputted by at least part of the port analyzing circuits as a first control signal according to the detecting signal. The I2C analyzing circuit analyzes a data flow for outputting a second control signal according to an address command related to an address message, a control command and an input data. The first multiplexer selects the first control signal or the second control to be outputted according to a testing signal.

Abstract: Methods and systems for supporting similar thermal devices may involve collecting, by a thermal module on a management controller of an information handling system, device information about an add-in card, determining whether the add-in card was previously defined by matching the device against a table, searching the table based on the determination that the add-in card was not previously defined, determining whether the add-in card is supported by finding a match in the table, and applying a thermal tier associated with the match in the table based on the determination that the add-in card is supported. The device information collected may involve at least two of a reseller part number, description, device identifier, sub device identifier, vendor identifier, sub vendor identifier, slot identifier, lane width, and auxiliary power indicator. The search of the table may involve at least one of the description, lane width, and sub vendor identifier.

Abstract: A data processing method and apparatus, the method comprising: storing, at a first memory location in a memory, a first copy of a set of data; storing, at a second memory location in a memory, a second copy of a set of data; comparing the first copy to the second copy so as to identify, within the first copy, a pointer, the pointer being located at a first data element of the first copy, the pointer specifying a second data element of the first copy; determining an offset for the identified pointer, the offset specifying a number of data elements between the first data element and the second data element; and modifying the first copy such that the pointer within the first copy specifies the second data element using only the first data element and the offset.

Abstract: A processor is provided that includes a first multiplication unit in a first data path of the processor, the first multiplication unit configured to perform single issue multiply instructions, and a second multiplication unit in the first data path, the second multiplication unit configured to perform single issue multiply instructions, wherein the first multiplication unit and the second multiplication unit are configured to execute respective single issue multiply instructions in parallel.

Abstract: An electronic device and a control method thereof are disclosed. The electronic device includes: a memory storing input data, and a processor including a first register file and a second register file storing index data corresponding to kernel data, wherein the processor is configured to: based on a first command being input, obtain offset information of valid data included in a part of the index data stored in the first register file, based on the number of pieces of the offset information being greater than or equal to a predetermined number, store data packed with the offset information in a unit of the predetermined number in the second register file, and obtain output data by performing an operation regarding the input data based on the packed data.

Abstract: A tile of an FPGA provides memory, arithmetic functions, or both. Connections directly between multiple instances of the tile are available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic and memory circuits are increased, operand sizes are increased, or both. By using the cascade connections, multiple tiles can be used together as a single, larger tile. Thus, implementations that need memories of different sizes, arithmetic functions operating on different sized operands, or both, can use the same FPGA without additional programming or waste. Using cascade communications, more tiles are used when a large memory is needed and fewer tiles are used when a small memory is needed and the waste is avoided.

Abstract: A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.

Abstract: An ALUA/aggregated switch latency reduction system includes a switch aggregation system coupling a server system including initiator devices to a storage system including target devices. The switch aggregation system includes a respective first switch device directly coupled to each of the target devices, and a respective second switch device directly coupled to each of the initiator devices. Each second switch device identifies an initiator device it is directly connected to, and transmits a respective first communication to each of the first switch devices that identifies that directly connected initiator device. When each second switch device receives a respective second communication from each of the first switch devices that identifies its directly connected target device, it identifies the first switch device directly connected to the target device that is in a session with its directly connected initiator device and, in response, causes packets to be forwarded to that first switch device.

Abstract: Embodiments of the present disclosure relate to a method, a device, and a computer program product for managing data transfer. A method for managing data transfer is provided, including: if determining that a request to transfer a data block between a memory and a persistent memory of a data storage system is received, obtaining a utilization rate of a central processing unit of the data storage system; and determining, from a first transfer technology and a second transfer technology and at least based on the utilization rate of the central processing unit, a target transfer technology for transferring a data block between the memory and the persistent memory, the first transfer technology transferring data through direct access to the memory, and the second transfer technology transferring data through the central processing unit. Therefore, the embodiments of the present disclosure can improve the data transfer performance of the storage system.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory and configured to: store first execution information that includes first processing for a plurality of data and second processing executed subsequently to the first processing; convert the first execution information into second execution information by making a start timing of the second processing earlier than an end timing of the first processing, under a restriction of an execution order in which a data read in the second processing is executed after a data write in the first processing for each of the plurality of data, on the basis of an order of data writes included in the first processing and an order of data reads included in the second processing; and output the second execution information.

Abstract: Extending fused multiply-add instructions, the method comprising: receiving an extended fused multiply-add (FMA) instruction indicating one or more operands of a fused multiply-add (FMA) operation and one or more transformations to be applied to the one or more operands; and performing, based on the extended FMA instruction, the one or more transformations and the FMA operation.

Abstract: Interrupt messages are sent from an interrupt controller to respective processor cores and data synchronization is managed among the processor cores. Each processor core includes a pipeline that includes a plurality of stages through which instructions of a program are executed, where stored order information indicates whether a state of the pipeline is in-order or out-of-order; and circuitry for receiving interrupt messages from the interrupt controller and performing an interrupt action in response to a corresponding interrupt message after ensuring that the order information indicates that the state of the pipeline is in-order when each interrupt action is performed. Managing the data synchronization includes generating a first interrupt message at an issuing processor core in response to a synchronization related instruction executed at the issuing processor core; and receiving the first interrupt message at each receiving processor core in a set of one or more receiving processor cores.

Abstract: Disclosed is a data processing system to receive a processing graph of an application. A compile time logic is configured to modify the processing graph and generate a modified processing graph. The modified processing graph is configured to apply a post-padding tiling after applying a cumulative input padding that confines padding to an input. The cumulative input padding pads the input into a padded input. The post-padding tiling tiles the padded input into a set of pre-padded input tiles with a same tile size, tiles intermediate representation of the input into a set of intermediate tiles with a same tile size, and tiles output representation of the input into a set of non-overlapping output tiles with a same tile size. Runtime logic is configured with the compile time logic to execute the modified processing graph to execute the application.

Abstract: Machine templates are described herein that provide for enhanced configuration and deployment of arrangements of physical computing components coupled over a communication fabric. In one example, a method includes presenting a user interface indicating a plurality of templates each specifying at least a predefined arrangement of physical computing components for inclusion in compute units, and receiving a user selection indicating a selected template among the plurality of templates to form a target compute unit. The method includes allocating to the target compute unit a set of physical computing components according to the selected template, and instructing a management entity to establish the target compute unit based at least on logical partitioning within a communication fabric communicatively coupling the set of physical computing components of the target compute unit.

Abstract: A cross-host multi-hypervisor system, including a plurality of host sites, each site including at least one hypervisor, each of which includes at least one virtual server, at least one virtual disk that is read from and written to by the at least one virtual server, a tapping driver in communication with the at least one virtual server, which intercepts write requests made by any one of the at least one virtual server to any one of the at least one virtual disk, and a virtual data services appliance, in communication with the tapping driver, which receives the intercepted write requests from the tapping driver, and which provides data services based thereon, and a data services manager for coordinating the virtual data services appliances at the site, and a network for communicatively coupling the plurality of sites, wherein the data services managers coordinate data transfer across the plurality of sites via the network.

Abstract: Many computing systems process data organized in a matrix format. For example, artificial neural networks (ANNs) perform numerous computations on data organized into matrices using conventional matrix arithmetic operations. One such operation, which is commonly performed, is the transpose operation. Additionally, many such systems need to process many matrices and/or matrices that are large in size. For sparse matrices that hold few significant values and many values that can be ignored, transmitting and processing all the values in such matrices is wasteful. Thus, techniques are introduced for storing a sparse matrix in a compressed format that allows for a matrix transpose operation to be performed on the compressed matrix without having to first decompress the compressed matrix. By utilizing the introduced techniques, more matrix operations can be performed than conventional systems.

Abstract: The present invention provides a pin multiplexer including a multiplexing circuit, a control circuit and a detecting circuit. The multiplexing circuit includes a first port, a second port and a third port, wherein the first port, the second port and the third port are coupled to a first device, a second device and a third device, respectively. The control circuit is configured to control the multiplexing circuit to operate in a first mode or a second mode, wherein when the multiplexing circuit operates in the first mode, the first port is coupled the second port; and when the multiplexing circuit operates in the second mode, the first port is coupled to the third port. When operating in the second mode, the detecting circuit detects a signal of the first port to generate a detection result for dynamically switching the data transmission direction between the third device and the first device.

Abstract: A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions that are executed by the at least one processor and configure the at least one processor to implement a device context device driver for forced detaching of an application from mapped devices. The device context device driver receives a command to detach an application, wherein the command specifies a process descriptor associated with the application. The device context device driver identifies a plurality of matching device context entries in a list of open device contexts maintained by the device context device driver that match the process descriptor. The device context device driver marks the plurality of matching device context entries as detached. The device context device driver invalidates mapped memory areas associated with the plurality of matching device context entries.

Abstract: The invention enables commissioning of field devices within a control system by implementing the steps of (i) detecting a connection event comprising a field device interfacing with an I/O port that is communicably coupled with the server, (ii) retrieving from a memory of the field device that is interfacing with the I/O port, a first field device identifier corresponding to the field device, (iii) retrieving from a non-transient memory database communicably coupled with the server, field device configuration data associated with the I/O port, wherein, the set of field device attributes includes a second field device identifier, and at least a segment of the second field device identifier is different from a corresponding segment of the first field device identifier, (iv) generating one of a translated first field device identifier and a translated second field device identifier, based on predefined translation data, (v) comparing the translated first field device identifier with the second field device ident

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for fetching data for an accelerator. The methods include detecting an attempt to access a first page of data that is not stored on a primary storage unit of the accelerator; and responsive to detecting the attempt to access the first page of data: assessing activity of the accelerator; determining, based on the assessed activity of the accelerator, a prefetch granularity size; and transferring a chunk of contiguous pages of data of the prefetch granularity size from a memory system connected to the accelerator into the primary storage unit, wherein the transferred chunk of contiguous pages of data include the first page of data.