Abstract: A method to compare first and second source data in a processor in response to a vector maximum with indexing instruction includes specifying first and second source registers containing first and second source data, a destination register storing compared data, and a predicate register. Each of the registers includes a plurality of lanes. The method includes executing the instruction by, for each lane in the first and second source register, comparing a value in the lane of the first source register to a value in the corresponding lane of the second source register to identify a maximum value, storing the maximum value in a corresponding lane of the destination register, asserting a corresponding lane of the predicate register if the maximum value is from the first source register, and de-asserting the corresponding lane of the predicate register if the maximum value is from the second source register.

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

Abstract: In an example embodiment, a framework to infer a user's value for a particular attribute based upon a multi-task machine learning process with uncertainty weighting that incorporates signals from multiple contexts is provided. In an example embodiment, the framework aims to measure a level of a user attribute under a certain context. Rather than attempting to devise a universal, one-size-fits-all value for the attribute, the framework acknowledges that the user's value for that attribute can vary depending on context and factors in the context under which the user's attribute levels are measured. Multiple contexts are defined depending on different situations where users and entities such as companies and organizations need to evaluate user attribute levels. Signals for attribute levels are then collected for each context. Machine learning models are utilized to estimate attribute values for different contexts. Multi-task deep learning is used to level attributes from different contexts.

Abstract: In a general aspect, hybrid quantum/classical algorithms are executed in a computing system. A first set of values representing a measurement of a reduced density matrix (RDM) is obtained. The first set of values is based on sampling quantum states generated by a quantum processor. A classical processor generates a second, different set of values to represent the measurement of the RDM. The second set of values is constructed based on the first set of values by a process that imposes one or more n-representability conditions on the second set of values to represent the measurement of the RDM.

Abstract: A method can be performed prior to implementation of a neural network by a processing unit. The neural network comprising a succession of layers and at least one operator applied between at least one pair of successive layers. A computational tool generates an executable code intended to be executed by the processing unit in order to implement the neural network. The computational tool generates at least one transfer function between the at least one pair of layers taking the form of a set of pre-computed values.

Abstract: An apparatus to facilitate machine learning matrix processing is disclosed. The apparatus comprises a memory to store matrix data one or more processors to execute an instruction to examine a message descriptor included in the instruction to determine a type of matrix layout manipulation operation that is to be executed, examine a message header included in the instruction having a plurality of parameters that define a two-dimensional (2D) memory surface that is to be retrieved, retrieve one or more blocks of the matrix data from the memory based on the plurality of parameters and a register file including a plurality of registers, wherein the one or more blocks of the matrix data is stored within a first set of the plurality of registers.

Abstract: This disclosure relates to a computing chip, a hashrate board, and a data processing apparatus. The computing chip includes a plurality of operation stages arranged in a pipeline configuration. Each operation stage includes: a first combinational logic circuit occupying a plurality of first cell points adjacent to each other, at least a portion of the first cell points being located in a first incomplete column; one or more second combinational logic circuits each occupying one or more second cell points, at least a portion of the second cell points being located in a second incomplete column; and a plurality of registers each occupying a plurality of third cell points, at least a portion of the third cell points being located in the first incomplete column or the second incomplete column. The first cell points, the second cell points, and third cell points occupy equal areas on the computing chip.

Abstract: Data channel parameter optimization with intelligent selection of initial data channel conditions and optimization algorithm hyperparameters for use of a black box optimizer to optimize one or more data channel parameters. It is currently identified that the initial data channel condition affects the ability of a black box optimizer to optimize data channel parameters. In turn, by use of an intelligent agent (e.g., employing artificial intelligence or machine learning) to iteratively select optimized initial data channel conditions, the optimization of the data channel may be improved. Moreover, the sensitivity of the data channel parameters may be determined, which allows for identification of a subset of data channel parameters that are varied in an optimization approach. This may result in improved performance of the optimization without sacrificing optimized performance of the data channel.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron comprises a dot product engine operative to: receive a set of weights; receive a set of data inputs based on a set of input data signals; and calculate the dot product of the set of data inputs and the set of weights to generate a dot product engine output. The neuron further comprises an activation function module arranged to apply an activation function to a signal indicative of the dot product engine output to generate a neuron output; and gain control circuitry. The gain control circuitry is operative to control: an input gain applied to the input data signals to generate the set of data inputs; and an output gain applied to the dot product engine output or by the activation function module. The output gain is selected to compensate for the applied input gain.

Abstract: An HDMI transmission device includes a packetizer circuit and a processor. A control method of controlling the HDMI transmission device includes performing a fixed rate link training, upon passing the fixed data rate link training, the processor transmitting an initial gap packet generation command to a controller of the packetizer circuit to output a selection signal to the packetizer circuit, so as to output an initial gap packet, when video data is not ready, continuously outputting the initial gap packet, when the video data is ready and a format change of the video data is detected or a signal abnormality unrelated to hot-plugging is detected, the processor transmitting a subsequent gap packet generation command to the controller to determine whether a block boundary is reached, and the controller switching the selection signal upon reaching the block boundary for the packetizer circuit to output the subsequent gap packet.

Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.

Abstract: A matrix multiplication circuit comprises a memory storage device, processing circuitry, a parallel multiply circuit, and buffer circuits. The parallel multiply circuit simultaneously performs a count of multiplies in a parallel multiplication operation. The buffer circuits include prefetch buffer circuits each having a storage array dimension corresponding to the count of multiplies in the parallel multiplication operation. The processing circuitry loads a first prefetch buffer circuit with values from the first matrix; fetches a value of the second matrix and, in parallel with the fetch, preload the second prefetch buffer circuit with another value from the first matrix; initiates a parallel multiply of the fetched value of the second matrix and the values in the first prefetch buffer circuit; and stores partial product results of the parallel multiply, including adding a current partial product result to a previously stored partial product result.

Abstract: Embodiments herein describe transferring ownership of data (e.g., cachelines or blocks of data comprising multiple cachelines) from a host to hardware in an I/O device. In one embodiment, the host and I/O device (e.g., an accelerator) are part of a cache-coherent system where ownership of data can be transferred from a home agent (HA) in the host to a local HA in the I/O device—e.g., a computational slave agent (CSA). That way, a function on the I/O device (e.g., an accelerator function) can request data from the local HA without these requests having to be sent to the host HA. Further, the accelerator function can indicate whether the local HA tracks the data on a cacheline-basis or by a data block (e.g., multiple cachelines). This provides flexibility that can reduce overhead from tracking the data, depending on the function's desired use of the data.

Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Abstract: A multi-processor system with processing elements, interspersed memory, and primary and secondary interconnection networks optimized for high performance and low power dissipation is disclosed. In the secondary network multiple message routing nodes are arranged in an interspersed fashion with multiple processors. A given message routing node may receive messages from other message nodes, and relay the received messages to destination message routing nodes using relative offsets included in the messages. The relative offset may specify a number of message nodes from the message node that originated a message to a destination message node.

Abstract: A computing device, comprising: a computing module, comprising one or more computing units; and a control module, comprising a computing control unit, and used for controlling shutdown of the computing unit of the computing module according to a determining condition. Also provided is a computing method. The computing device and method have the advantages of low power consumption and high flexibility, and can be combined with the upgrading mode of software, thereby further increasing the computing speed, reducing the computing amount, and reducing the computing power consumption of an accelerator.

Abstract: A processor system comprises a first and second group of registers and a hardware channel convolution processor unit. The first group of registers is configured to store data elements of channels of a portion of a convolution data matrix. Each register stores at least one data element from each channel. The second group of registers is configured to store data elements of convolution weight matrices including a separate convolution weight matrix for each channel. Each register stores at least one data element from each convolution weight matrix. The hardware channel convolution processor unit is configured to multiply each data element in the first group of registers with a corresponding data element in the second group of registers and sum together the multiplication results for each specific channel to determine corresponding channel convolution result data elements in a corresponding channel convolution result matrix.

Abstract: Technologies for providing I/O channel abstraction for accelerator device kernels include an accelerator device comprising circuitry to obtain availability data indicative of an availability of one or more accelerator device kernels in a system, including one or more physical communication paths to each accelerator device kernel. The circuitry is also configured to determine whether to establish a logical communication path between a kernel of the present accelerator device and another accelerator device kernel and establish, in response to a determination to establish the logical communication path as a function of the obtained availability data, the logical communication path between the kernel of the present accelerator device and the other accelerator device kernel.

Abstract: A neural network apparatus that is configured to process an operation includes neural network circuitry configured to receive a first input of an n-bit activation, store a second input of an m-bit weight, perform a determination whether to perform an operation on an ith bit of the first input and a jth bit of the second input, output an operation value of an operation performed on the ith bit of the first input and the jth bit of the second input based on the determination, and produce an operation value of the operation based on the determination.

Abstract: Disclosed is a convolution operator system for performing a convolution operation concurrently on an image. An input router receives image data. A controller allocates image data to a set of computing blocks based on the size of the image data and number of available computing blocks. Each computing block produces a convolution output corresponding to each row of the image. The controller allocates a plurality of group having one or more computing blocks to generate a set of convolution output. Further, a pipeline adder aggregates the set of convolution output to produce an aggregated convolution output. An output router transmits either the convolution output or the aggregated convolution output for performing subsequent convolution operation to generate a convolution result for the image data.