Patents Examined by Fazli Erdem
  • Patent number: 11450826
    Abstract: A light emitting device includes: a first electrode and a second electrode facing each other, an emissive layer disposed between the first electrode and the second electrode and including a quantum dot, an electron auxiliary layer disposed between the emissive layer and the second electrode and including a plurality of nanoparticles, and a polymer layer between a portion of the second electrode and the electron auxiliary layer, wherein the nanoparticles include a metal oxide including zinc, wherein the second electrode has a first surface facing a surface of the electron auxiliary layer and a second surface opposite to the first surface, and the polymer layer is disposed on a portion of the second surface and a portion of the surface of the electron auxiliary layer, and wherein the polymer layer includes a polymerization product of a thiol compound and an unsaturated compound having at least two carbon-carbon unsaturated bonds.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: September 20, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Ho Kim, Won Sik Yoon, Jeong Hee Lee, Eun Joo Jang, Oul Cho
  • Patent number: 11444192
    Abstract: There is disclosed a method for manufacturing a MOSFET with lateral channel in SiC, said MOSFET comprising simultaneously formed n type regions (7) comprising an access region (7a) and a JFET region (7b) defining the length of the MOS channel (17), and wherein the access region (7a) and the JFET region (7b) are formed by ion implantation by using one masking step. The design is self-aligning so that the length of the MOS channel (17) is defined by simultaneous creating n-type regions on both sides of the channel (17) using one masking step. Any misalignment in the mask is moved to other less critical positions in the device. The risk of punch-through is decreased compared to the prior art. The current distribution becomes more homogenous. The short-circuit capability increases. There is lower Drain-Source specific on-resistance due to a reduced MOS channel resistance. There is a lower JFET resistance due to the possibility to increase the JFET region doping concentration.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: September 13, 2022
    Assignee: II-VI DELAWARE INC.
    Inventors: Adolf Schöner, Sergey Reshanov, Nicolas Thierry-Jebali, Hossein Elahipanah
  • Patent number: 11437505
    Abstract: Even when a stress is applied due to energization or switching operation, a connection state of electrode layers can be appropriately maintained. A semiconductor device includes a semiconductor layer of first conductivity type, an upper surface structure formed on a surface layer of the semiconductor layer, and an upper surface electrode formed over the upper surface structure. The upper surface electrode includes a first electrode formed on an upper surface of the semiconductor layer, and a second electrode formed over an upper surface of the first electrode. The first concave portion is formed on the upper surface of the first electrode. A side surface of the first concave portion has a tapered shape. The second electrode is formed over the upper surface of the first electrode including an inside of the first concave portion.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 6, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunari Nakata, Kensuke Taguchi
  • Patent number: 11437463
    Abstract: According to one embodiment, a display device comprises a flexible substrate, a first insulating film disposed on the flexible substrate, a switching element disposed on the first insulating film, a signal wiring electrically connected with the switching element, a first organic film disposed on the signal wiring, a connection wiring disposed on the first organic film, a second organic film disposed on the connection wiring and a pad electrode disposed on the second organic film. The connection wiring is located between the first organic film and the second organic film and is in contact with the first organic film and the second organic film.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: September 6, 2022
    Assignee: Japan Display Inc.
    Inventor: Yasushi Kawata
  • Patent number: 11437422
    Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Bo-Tsung Tsai
  • Patent number: 11424326
    Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: August 23, 2022
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio Nakabayashi, Tatsuo Shimizu, Toshihide Ito, Chiharu Ota, Johji Nishio
  • Patent number: 11417528
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a carbon structure on a handle substrate at a first surface of the handle substrate. The method further includes attaching a first surface of a semiconductor substrate to the first surface of the handle substrate. The method further includes processing the semiconductor substrate and performing a separation process to separate the handle substrate from the semiconductor substrate. The separation process comprises modifying the carbon structure.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Francisco Javier Santos Rodriguez, Roland Rupp, Hans-Joachim Schulze
  • Patent number: 11417747
    Abstract: In an example, a transistor device is provided. The transistor device includes a plurality of transistor cells each including a gate electrode and each at least partially integrated in a semiconductor body that includes a wide bandgap semiconductor material. The transistor device includes a gate pad arranged on top of the semiconductor body, and a plurality of gate runners each arranged on top of the semiconductor body and each connected to gate electrodes of at least some of the plurality of transistor cells. Each gate runner of the plurality of gate runners has a longitudinal direction, and at least one of the gate runners includes at least a section in which a resistivity per area increases in the longitudinal direction as a distance to the gate pad along the gate runner increases.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Ralf Siemieniec, Frank Wolter
  • Patent number: 11411142
    Abstract: A light emitting diode chip includes a substrate; a first conductivity type semiconductor layer disposed on the substrate; a mesa; a transparent electrode; a contact electrode; a current spreader; a first insulating reflection layer; a first pad electrode and a second pad electrode; and a second insulating reflection layer. The first insulating reflection layer covers one end of the substrate, the first conductivity type semiconductor layer, the mesa, the transparent electrode. The second insulating reflection layer is disposed on an opposite end of the substrate and includes a structure of a distributed Bragg reflector (DBR).
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 9, 2022
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jin Woong Lee, Kyoung Wan Kim, Tae Jun Park, Sang Won Woo
  • Patent number: 11411093
    Abstract: In a method of manufacturing a silicon carbide semiconductor device that is a silicon carbide diode having a JBS structure including a mixture of a Schottky junction and a pn junction and that maintains low forward voltage through a SBD structure and enhances surge current capability, nickel silicide films are formed in an oxide film by self-alignment by causing a semiconductor substrate and a metal material film to react with one another through two sessions of heat treatment including a low-temperature heat treatment and a high-temperature heat treatment, the metal material film including sequentially a first nickel film, an aluminum film, and a second nickel film, the first nickel film being in contact with an entire area of a connecting region of a FLR and p-type regions respectively exposed in openings of the oxide film.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 9, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahito Kojima, Naoyuki Ohse
  • Patent number: 11404524
    Abstract: A display panel, a display module, and an electronic device are provided. The display panel includes a third metal layer including a signal line, and a conductive layer including a connection portion. The connection portion is connected to the signal line. A pixel definition layer is disposed on the conductive layer, and the pixel definition layer includes a first opening region and a second opening region. A cathode is disposed in the second opening region and disposed on the pixel definition layer. The cathode is connected to the connection portion.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: August 2, 2022
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shiqiang Huang, Xing Ming, Qi Cao
  • Patent number: 11397354
    Abstract: A lighting device includes a lighting unit emitting an output light having a light spectrum. The light spectrum in a range from 520 nm to 780 nm has a main peak, and the light spectrum in a range from 400 nm to 470 nm has a sub peak with a maximum intensity at a first wavelength. A first sub peak integral is an integral of the light spectrum calculated from a wavelength of the first wavelength minus 20 nm to the first wavelength. A second sub peak integral is an integral of the light spectrum calculated from the first wavelength to a wavelength of the first wavelength plus 20 nm. A ratio of the first sub peak integral to the second sub peak integral is in a range from 20% to 98%.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: July 26, 2022
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai
  • Patent number: 11393922
    Abstract: A semiconductor device includes a semiconductor substrate. A drift region is disposed in the semiconductor substrate. The drift region has a first conductivity type. A body region is disposed in the semiconductor substrate, adjacent to the drift region. The body region has a second conductivity type. A drain region is disposed opposite to the body region in the drift region. A drain isolation insulating film is disposed in a portion adjacent to the drain region of the drift region. A gate insulating film is disposed on the semiconductor substrate and is extended over a portion of the body region and a portion of the drift region. A gate electrode is disposed on the gate insulating film and the gate electrode has at least one closed-type opening.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyuok Lee, Jaehyun Yoo, Jungkyung Kim, Juhyeon Song, Suyeon Cho, Wonpyo Hong
  • Patent number: 11393921
    Abstract: A high-voltage semiconductor device includes a substrate, a first insulating structure, a gate, a drain region, a source region and a doped region. The substrate has a first conductive type, and the first insulating structure is disposed on the substrate. The drain region and the source region are disposed in the substrate. The source region has a first portion and a second portion. The first portion has the second conductive type and the second portion has the first conductive type. The gate is disposed on the substrate, between the source region and the drain region to partially cover a side of the first insulating structure. The doped region is disposed in the substrate and has a first doped region and a second doped region, and the first doped region and the second doped region both include the first conductive type and separately disposed under the first insulating structure.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: July 19, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Hung-Chih Tan, Hsing-Chao Liu, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11393911
    Abstract: A semiconductor device has: a semiconductor substrate; a drift layer of a first conductivity type; a well region of a second conductivity type; a high-concentration region of the second conductivity type, a source region of the first conductivity type; an insulating film provided on the drift layer; a first contact metal film in contact with the source region and the high-concentration region through a first opening provided in the insulating film; and a second contact metal film formed on a surface of the first contact metal film and contacting the high-concentration region through a second opening provided in the first contact metal film; a source electrode film formed on a surface of a contact metal layer including the first contact metal film and the second contact metal film. The first contact metal film includes titanium nitride, and the second contact metal film includes titanium.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: July 19, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Teppei Takahashi, Tetsuto Inoue, Akihiko Sugai, Takashi Mochizuki, Shunichi Nakamura
  • Patent number: 11380764
    Abstract: The purpose of the present invention is to provide a semiconductor device comprising an epitaxial layer formed on a SiC substrate, and a CMOS formed in the top part of the epitaxial layer, wherein growth of any defects present at the interface between the SiC substrate and the epitaxial layer is suppressed, and the reliability of the semiconductor device is improved. As a means to achieve the foregoing, a semiconductor device is formed such that the distance from a p-type diffusion layer to the interface between an n-type epitaxial layer and an n-type semiconductor substrate is larger than the thickness of a depletion layer that extends from the p-type diffusion layer to the back side of the n-type semiconductor substrate in response to the potential difference between a substrate electrode and another substrate electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 5, 2022
    Assignee: HITACHI, LTD.
    Inventors: Masahiro Masunaga, Shintaroh Sato, Akio Shima, Digh Hisamoto
  • Patent number: 11380756
    Abstract: A silicon carbide device includes a silicon carbide body including a source region of a first conductivity type, a cathode region of the first conductivity type and separation regions of a second conductivity type. A stripe-shaped gate structure extends along a first direction and adjoins the source region and the separation regions. The silicon carbide device includes a first load electrode. Along the first direction, the cathode region is between two separation regions of the separation regions and at least one separation region of the separation regions is between the cathode region and the source region. The source region and the first load electrode form an ohmic contact. The first load electrode and the cathode region form a Schottky contact.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 5, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Caspar Leendertz, Rudolf Elpelt, Romain Esteve, Thomas Ganner, Jens Peter Konrath, Larissa Wehrhahn-Kilian
  • Patent number: 11374096
    Abstract: The present disclosure provides a high voltage semiconductor device includes a substrate, a first well region, a second well region, a source, a drain, a first electrode structure and a second electrode structure. The first well region and the second well region are disposed in the substrate, and which includes a first conductive type and a second conductive type which are complementary with each other. The source and the drain are respectively disposed within the first well region and the second well region. The first electrode structure and the second electrode structure are both disposed on the substrate, and the distance between the top surface of an electrode of the first electrode structure and the top surface of the substrate includes a first height and a second height which are different from each other.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: June 28, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chung-Ren Lao, Kuan-I Ho, Kuo-Chien Hsu, Che-Hua Chang, Hsiao-Ying Yang, Chih-Cherng Liao
  • Patent number: 11367785
    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 21, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Jing Zhu, Ankang Li, Long Zhang, Weifeng Sun, Shengli Lu, Longxing Shi
  • Patent number: 11367661
    Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 21, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Yang Beom Kang, Kang Sup Shin