Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

Abstract: A selector device including a first metal electrode layer, a second metal electrode layer and a switching layer disposed between the first metal electrode layer and the second metal electrode layer. The switching layer is a stacked assembly of ABA, BAB, AB or BA, where A is an ion supply layer, and B is a conversion layer. The ion supply layer includes a chalcogenide metal material having a metal atomic content of more than 0% and not more than 50% with respect to the chalcogenide metal material. The conversion layer includes a chalcogenide material.

Abstract: A SiC MOSFET device with alternating p-well widths, including an undulating channel, is described. The undulating channel provides current paths of multiple widths, which enables optimization of on-resistance, transconductance, threshold voltage, and channel length. The multi-width p-well region further defines corresponding multi-width Junction FETs (JFETs). The multi-width JFETs enable improved response to a short-circuit event. A high breakdown voltage is obtained by distributing a high electric field in a JFET of a first width into a JFET of a second width.

Abstract: A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Abstract: A method and vertical FET device fabricated in GaN or other suitable material. The device has a selective area implant region comprising an activated impurity configured from a bottom portion of a recessed regions, and substantially free from ion implant damage by using an annealing process. A gate region is configured from the selective area implant region, and each of the recessed regions is characterized by a depth configured to physically separate an n+ type source region and the p-type gate region such that a low reverse leakage gate-source p-n junction is achieved. An extended drain region is configured from a portion of an n? type GaN region underlying the recessed regions. An n+ GaN region is formed by epitaxial growth directly overlying the backside region of the GaN substrate and a backside drain contact region configured from the n+ type GaN region overlying the backside region.

Abstract: Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm?Lxr?0.20 ?m holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.

Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, a first oxide layer, a field plate, and a second oxide layer. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure respectively. The first oxide layer includes a first portion disposed between the gate structure and the semiconductor substrate and a second portion disposed between the gate structure and the drain region. The field plate is partly disposed above the gate structure and partly disposed above the second portion of the first oxide layer. The second oxide layer includes a first portion disposed between the field plate and the gate structure and a second portion disposed between the field plate and the second portion of the first oxide layer.

Abstract: A semiconductor structure and a method for forming the same are provided in embodiments of the present disclosure. The forming method includes: providing a base; forming a trench in the base, and forming a first dielectric layer on the bottom surface and side walls of the trench; forming a conductor layer, the conductor layer covering the first dielectric layer on the bottom surface of the trench; forming a second dielectric layer in the trench on the conductor layer; and forming a drift region on a side, provided with the trench, of the base. The forming method can improve the breakdown voltage of an LDMOS device and also reduce the Ron of the LDMOS device, thereby improving the performance of the LDMOS device.

Abstract: A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.

Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

Abstract: A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

Abstract: A semiconductor device includes a substrate, a dielectric isolation structure disposed on the substrate, a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure, first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin, a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins, and an epitaxial feature over the semiconductor fin. The epitaxial feature has a bottom portion laterally between the first and second dielectric fins.

Abstract: An example image sensor structure includes an image layer. The image layer includes an array of light detectors disposed therein. A device stack is disposed over the image layer. An array of light guides is disposed in the device stack. Each light guide is associated with at least one light detector of the array of light detectors. A passivation stack is disposed over the device stack. The passivation stack includes a bottom surface in direct contact with a top surface of the light guides. An array of nanowells is disposed in a top layer of the passivation stack. Each nanowell is associated with a light guide of the array of light guides. A crosstalk blocking metal structure is disposed in the passivation stack. The crosstalk blocking metal structure reduces crosstalk within the passivation stack.

Abstract: A semiconductor package includes a first semiconductor chip having a first surface and a second surface opposite to each other, a second semiconductor chip on the second surface of the first semiconductor chip and electrically connected to the first semiconductor chip, and a molding pattern bordering side surfaces of the first semiconductor chip and side surfaces of the second semiconductor chip. At least a portion of the first surface of the first semiconductor chip is free of the molding pattern. A glass pattern is on the first surface of the first semiconductor chip.

Abstract: A display substrate and a driving method thereof are provided. The display substrate includes a base substrate containing a monocrystalline silicon layer, a thickness of the monocrystalline silicon layer being less than that of the base substrate; an array circuit layer, disposed on the base substrate and including a plurality of transistors, each of which has an active layer inside the monocrystalline silicon layer; and a plurality of light-emitting elements, located at a side of the array circuit layer away from the base substrate. The array circuit layer includes a scan driving circuit, a data driving circuit and a plurality of pixel sub-circuits, and the plurality of pixel sub-circuits are connected to the plurality of light-emitting elements, respectively, to form a plurality of sub-pixels.

Abstract: A transfer-printable (e.g., micro-transfer-printable) device source wafer comprises a growth substrate comprising a growth material, a plurality of device structures comprising one or more device materials different from the growth material, the device structures disposed on and laterally spaced apart over the growth substrate, each device structure comprising a device, and a patterned dissociation interface disposed between each device structure of the plurality of device structures and the growth substrate. The growth material is more transparent to a desired frequency of electromagnetic radiation than at least one of the one or more device materials. The patterned dissociation interface has one or more areas of relatively greater adhesion each defining an anchor between the growth substrate and a device structure of the plurality of device structures and one or more dissociated areas of relatively lesser adhesion between the growth substrate and the device structure of the plurality of device structures.

Abstract: An integrated circuit has a P-type substrate and an N-type LDMOS transistor. The LDMOS transistor includes a boron-doped diffused well (DWELL-B) and an arsenic-doped diffused well (DWELL-As) located within the DWELL-B. A first polysilicon gate having first sidewall spacers and a second polysilicon gate having second sidewall spacers are located over opposite edges of the DWELL-B. A source/IBG region includes a first source region adjacent the first polysilicon gate, a second source region adjacent the second polysilicon gate, and an integrated back-gate (IBG) region located between the first and second source regions. The first source region and the second source region each include a lighter-doped source sub-region, the IBG region including an IBG sub-region having P-type dopants, and the source/IBG region includes a heavier-doped source sub-region.

Abstract: A finFET device and methods of forming a finFET device are provided. The device includes a fin and a capping layer over the fin. The device also includes a gate stack over the fin, the gate stack including a gate electrode and a gate dielectric. The gate dielectric extends along sidewalls of the capping layer. The device further includes a gate spacer adjacent to sidewalls of the gate electrode, the capping layer being interposed between the gate spacer and the fin.

Abstract: A display apparatus includes a substrate including a display area and a non-display area disposed around the display area, a driving circuit disposed in the non-display area, a first conductive line extending in a first direction and disposed in the non-display area, a second conductive line extending in the first direction and disposed on the first conductive line, and a third conductive line extending in the first direction and disposed on the second conductive line, wherein the second conductive line overlaps the first conductive line by a first width or is spaced apart from the first conductive line by a first distance in a plan view, and the third conductive line overlaps the first conductive line by a second width or is spaced apart from the first conductive line by a second distance in the plan view.

Abstract: An electronic device stretchable from a first state to a second state includes a substrate, a plurality of light emitting groups, and a plurality of signal pads. The substrate has a first region and a second region. The light emitting groups are disposed on the first region. The signal pads are disposed on the second region. When the electronic device is stretched from the first state to the second state, the first region has a first stretching ratio (R1) and the second region has a second stretching ratio (R2), and the first stretching ratio (R1) is greater than the second stretching ratio (R2).