Abstract: A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

Abstract: A display substrate and a display device are provided in the present invention. The display substrate includes a base substrate, and a positive power supply line, a negative power supply line and a first dam which are on the base substrate. The base substrate includes a display region and a peripheral region arranged around the display region. The positive power supply line, the negative power supply line and the first dam are in the peripheral region, and the first dam is arranged around the display region. At least in a corresponding region between the positive power supply line and the negative power supply line, a protruding structure is on a side of the first dam proximal to the display region.

Abstract: Semiconductor device including first semiconductor layer of a first conductivity type, second semiconductor layer of a second conductivity type at a surface of the first semiconductor layer, third semiconductor layer of the first conductivity type selectively provided at a surface of the second layer, and gate electrode embedded in a trench via a gate insulating film. The trench penetrates the second and third layers, and reaches the first layer. A thermal oxide film on the third layer has a thickness less than that of the gate insulating film. Also are an interlayer insulating film on the thermal oxide film, barrier metal on an inner surface of a contact hole selectively opened in the thermal oxide film and the interlayer insulating film, metal plug embedded in the contact hole on the barrier metal, and electrode electrically connected to the second and third layers via the barrier metal and the metal plug.

Abstract: A semiconductor device includes a semiconductor layer structure of a wide band-gap semiconductor material. The semiconductor layer structure includes a drift region having a first conductivity type and a well region having a second conductivity type. A plurality of segmented gate trenches extend in a first direction in the semiconductor layer structure. The segmented gate trenches include respective gate trench segments that are spaced apart from each other in the first direction with intervening regions of the semiconductor layer structure therebetween. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes: a substrate (10); a semiconductor layer (20) disposed on a main surface of this substrate (10); and a first main electrode (30) and a second main electrode (40), which are disposed on the substrate (10) separately from each other with the semiconductor layer (20) sandwiched therebetween and are individually end portions of a current path of a main current flowing in an on-state. The semiconductor layer (20) includes: a first conductivity-type drift region (21) through which a main current flows; a second conductivity-type column region (22) that is disposed inside the drift region (21) and extends in parallel to a current path; and an electric field relaxation region (23) that is disposed in at least a part between the drift region (21) and the column region (22) and is either a low-concentration region in which an impurity concentration is lower than in the same conductivity-type adjacent region or a non-doped region.

Abstract: An array substrate, its manufacturing method, and a display apparatus are provided. The array substrate having a substrate, includes: a monocrystalline silicon substrate employed as the substrate including a central display area, a first peripheral area, and a second peripheral area; substrate circuits integrated with a scan drive circuit in the first peripheral area, a data drive circuit in the second peripheral area, and a plurality of pixel circuits in the central display area; a plurality of scan lines in the central display area and coupled to the scan drive circuit; and a plurality of data lines in the central display area and coupled to the data drive circuit. The scan drive circuit, the data drive circuit, and the plurality of pixel circuits include a plurality of transistors, each of which has an active region inside the monocrystalline silicon layer.

Abstract: A semiconductor device comprises: a substrate; a well region provided in the substrate, having a second conductivity type; source regions having a first conductivity type; body tile regions having the second conductivity type, the source regions and the body tie regions being alternately arranged in a conductive channel width direction so as to form a first region extending along the conductive channel width direction, and a boundary where the edges of the source regions and the edges of the body tie regions are alternately arranged being formed on two sides of the first region; and a conductive auxiliary region having the first conductivity type, provided on at least one side of the first region, and directly contacting the boundary, a contact part comprising the edge of at least one source region on the boundary and the edge of at least one body tie region on the boundary.

Abstract: A semiconductor device includes: an n?-type epitaxial layer having an element main surface; a p?-type body region, an n+-type source region, and n+-type drain regions; and a gate electrode including a second opening and first openings formed in a portion separated from the second opening toward the drain regions, wherein the body region selectively has a second portion exposed to the first openings of the gate electrode, and wherein the semiconductor device further includes a p+-type body contact region formed in the portion of the body region exposed to the first openings and having an impurity concentration higher than an impurity concentration of the body region.

Abstract: A manufacturing method of a semiconductor device includes the following steps. A first inter-metal dielectric (IMD) layer is formed on a substrate. A cap layer is formed on the first IMD layer. A connection structure is formed on the substrate and penetrates the cap layer and the first IMD layer. A magnetic tunnel junction (MTJ) stack is formed on the connection structure and the cap layer. A patterning process is performed to the MTJ stack for forming a MTJ structure on the connection structure and removing the cap layer. A spacer is formed on a sidewall of the MTJ structure and a sidewall of the connection structure. A second IMD layer is formed on the first IMD layer and surrounds the MTJ structure. The dielectric constant of the first IMD layer is lower than the dielectric constant of the second IMD layer.

Abstract: An integrated circuit (IC) having a fin field effect transistor (FinFET) includes a substrate with a fin extending from a surface of the substrate. The fin includes a source region, a drain region, a drift region, and field plating oxide layer. The drift region is adjacent the drain region. The field plating oxide layer is on a first side, a second side, and a third side of the drift region.

Abstract: A display device includes a substrate, data lines arranged on the substrate, the data lines to which data voltages are applied, scan lines arranged on the substrate, the scan lines to which scan signals are applied, and a pixel connected to one of the data lines and at least one of the scan lines. The pixel includes a light emitting element, a driving transistor which supplies a driving current flowing between a first electrode and a second electrode to the light emitting element in accordance with the data voltage of the data line applied to a gate electrode, a first transistor between the gate electrode and second electrode of the driving transistor, a shielding electrode overlapping at least a part of the first transistor in a thickness direction of the substrate. The shielding electrode does not overlap the data lines in the thickness direction of the substrate.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, the image sensor comprises a plurality of pixel regions disposed within a substrate and respectively comprising a photodiode configured to receive radiation that enters the substrate from a back-side. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions surrounding the photodiode. The BDTI structure extends from the back-side of the substrate to a first depth within the substrate. A multiple deep trench isolation (MDTI) structure is disposed at inner regions of the pixel regions overlying the photodiode. The MDTI structure extends from the back-side of the substrate to a second depth within the substrate smaller than the first depth. The MDTI structure is a continuous integral unit having a ring shape.

Abstract: The present disclosure provides an antenna package structure and an antenna packaging method. The package structure includes a rewiring layer, wherein the rewiring layer comprises a first dielectric layer and a first metal wiring layer in the first dielectric layer; metal connecting column, formed on the first metal wiring layer of the rewiring layer; a packaging layer, disposed on the rewiring layer, an antenna metal layer, formed on the packaging layer, an antenna circuit chip, bonded to the first metal layer of the rewiring layer, and electrically connected to the antenna metal layer through the metal connecting column; and a metal bump, formed on the first metal wiring layer of the rewiring layer, to achieve electrical lead-out of the rewiring layer.

Abstract: A semiconductor device includes a semiconductor base body, and a first main electrode and a second main electrode provided on the semiconductor base body. The semiconductor base body includes a drift region of a first conductivity type through which a main current flows, a column region of a second conductivity type arranged adjacent to the drift region in parallel to a current passage of the main current, a second electrode-connection region of the first conductivity type electrically connected to the second main electrode, and a low-density electric-field relaxation region of the first conductivity type having a lower impurity concentration than the drift region and arranged between the second electrode-connection region and the column region.

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Abstract: A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.

Abstract: A semiconductor device includes a substrate includes a first layer and a second layer over the first layer, a bump disposed over the second layer, a molding disposed over the second layer and surrounding the bump, and a retainer disposed over the second layer, wherein the retainer is disposed between the molding and a periphery of the substrate. Further, a method of manufacturing a semiconductor device includes providing a substrate, disposing several bumps on the substrate, disposing a retainer on the substrate and surrounding the bumps, and disposing a molding between the bumps and the retainer.

Abstract: A semiconductor device includes a semiconductor device provided on a semiconductor substrate and an ohmic electrode provided on a back surface of the semiconductor device and containing a nickel silicide and a molybdenum carbide, or the nickel silicide and a titanium carbide. The ohmic electrode is configured by first regions where a silicide is thick and second regions where the silicide is thin; a ratio of an arithmetic area of the second regions to an arithmetic area of the ohmic electrode is in a range from 10% to 30% in a plan view.

Abstract: A SiC SJ trench MOSFET having first and second type gate trenches for formation of gate electrodes and super junction regions is disclosed. The gate electrodes are disposed into the first type gate trenches having a thick oxide layer on trench bottom. The super junction regions are formed surrounding the second type gate trenches filled up with the thick oxide layer. The device further comprises gate oxide electric field reducing regions adjoining lower surfaces of body regions and space apart from the gate trenches.

Abstract: A method for forming a semiconductor device includes implanting first ions and second ions into a p-type silicon carbide layer from a first main side to form an implantation layer at the first main side. The implanting is performed by plasma immersion ion implantation in which the p-type silicon carbide layer is immersed in a plasma comprising the first ions and the second ions. The first ions can be ionized aluminum atoms and the second ions are different from the first ions.