Patents Examined by Fernando L. Toledo
  • Patent number: 11456373
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 11456256
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric structure, an electrical insulating and thermal conductive layer and a circuit layer. The electrical insulating and thermal conductive layer is disposed over the semiconductor substrate. The dielectric structure is disposed over the electrical insulating and thermal conductive layer, wherein a thermal conductivity of the electrical insulating and thermal conductive layer is substantially greater than a thermal conductivity of the dielectric structure. The circuit layer is disposed in the dielectric structure.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: September 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hang Tung, Chen-Hua Yu, Tung-Liang Shao, Su-Chun Yang, Wen-Lin Shih
  • Patent number: 11444122
    Abstract: A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: September 13, 2022
    Inventor: Jae hoon Kim
  • Patent number: 11435393
    Abstract: Described herein are techniques related to a semiconductor fabrication process that facilitates the enhancement of systemic conformities of patterns of the fabricated semiconductor wafer. A semiconductor wafer with maximized systemic conformities of patterns will maximize the electrical properties and/or functionality of the electronic devices formed as part of the fabricated semiconductor wafer. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: September 6, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Carlos A. Fonseca, Nathan Ip, Joel Estrella
  • Patent number: 11437327
    Abstract: The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Han-Ping Pu, Hsiao-Wen Lee
  • Patent number: 11437335
    Abstract: Integrated circuit (IC) packages employing a thermal conductive semiconductor package substrate with die region split and related fabrication methods are disclosed. The package substrate includes a die split where metal contacts in one or more dielectric layers of the package substrate underneath the IC die(s) are thicker (e.g., in a core die region) than other metal contacts (e.g., in a peripheral die region) in the dielectric layer. This facilitates higher thermal dissipation from the IC die(s) through the thicker metal contacts in the package substrate. Cross-talk shielding of the package substrate may not be sacrificed since thinner metal contacts of the package substrate that carry high speed signaling can be of lesser thickness than the thicker metal contacts that provide higher thermal dissipation.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: September 6, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Aniket Patil, Bohan Yan, Dongming He
  • Patent number: 11430787
    Abstract: Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Cory C. Bomberger, Anand S. Murthy
  • Patent number: 11430871
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 30, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11424383
    Abstract: A semiconductor device includes: a first semiconductor region; and a first electrode on the first semiconductor region; wherein first semiconductor region includes a first layer and a second layer, the second layer includes a first portion and a second portion adjacent to the first portion, the first portion has a first thickness, the second portion has a second thickness less than the first thickness, the first layer includes a first material and a first dopant, the first material includes multiple elements, the first dopant has a first concentration, the second layer includes a second material and a second dopant, the second material includes multiple elements, the second dopant has a second concentration, one of the elements of the first material of the first layer is different from the elements of the second material of the second layer.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 23, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Tzu-Chieh Hu, Wei-Chieh Lien, Chen Ou, Chia-Ming Liu, Tzu-Yi Chi
  • Patent number: 11424192
    Abstract: A component-embedded substrate includes a first wiring substrate, an electronic component provided on the first wiring substrate, an intermediate wiring substrate provided around the electronic component on the first wiring substrate and connected to the first wiring substrate via a first connection member, a second wiring substrate provided above the first wiring substrate, the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second connection member, and an encapsulating resin filled between the first wiring substrate and the second wiring substrate and covering the electronic component and the intermediate wiring substrate. Side surfaces of the intermediate wiring substrate are entirely covered by the encapsulating resin.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: August 23, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Norio Yamanishi, Takeshi Meguro
  • Patent number: 11417613
    Abstract: A semiconductor package includes: a frame substrate having a plurality of wiring layers and a cavity; an adhesive member disposed at the bottom of the cavity; a semiconductor chip disposed in the cavity, with a connection pad on an upper surface and the lower surface in contact with the adhesive member; a first conductive bump disposed on the connection pad; a second conductive bump disposed on the uppermost of the plurality of wiring layers; an insulating post disposed in the cavity and whose lower surface contacts the adhesive member; an encapsulant filling the cavity and covering side surfaces of the first and second conductive bumps and the insulating post’ and a redistribution structure disposed on the encapsulant, including a redistribution layer electrically connected to the first and second conductive bumps, wherein the insulating post includes a material having a greater hardness than that of the first and second conductive bumps.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jingu Kim, Shanghoon Seo, Sangkyu Lee, Jeongho Lee
  • Patent number: 11417571
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 16, 2022
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu
  • Patent number: 11411034
    Abstract: A solid-state imaging device according to the present disclosure includes a photoelectric conversion film that is provided outside a semiconductor substrate on a pixel-by-pixel basis, performs photoelectric conversion on light having a predetermined wavelength range, and transmits light having wavelength ranges other than the predetermined wavelength range, and a photoelectric conversion region that is provided inside the semiconductor substrate on a pixel-by-pixel basis and performs photoelectric conversion on the light having the wavelength ranges, the light having the wavelength ranges having passed through the photoelectric conversion film. The photoelectric conversion film includes a film having an avalanche function.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 9, 2022
    Assignee: SONY CORPORATION
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Otake
  • Patent number: 11411194
    Abstract: A light-emitting device (20) includes a first light-emitting member (10a) and a second light-emitting member (10b). Each of the first light-emitting member (10a) and the second light-emitting member (10b) includes a first surface (12) and a second surface (14), and light is emitted from the first surface (12). The first light-emitting member (10a) includes a first region (16a) and a second region (16b), the first region (16a) of the first light-emitting member (10a) being located on the second surface (14) side of the second light-emitting member (10b) and the second region (16b) of the first light-emitting member (10a) being located on the first surface (12) side of the second light-emitting member (10b).
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 9, 2022
    Assignee: PIONEER CORPORATION
    Inventors: Ayako Yoshida, Takashi Chuman, Makoto Matsukawa, Takeru Okada, Chihiro Harada, Akira Hirasawa
  • Patent number: 11411038
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: August 9, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Patent number: 11404347
    Abstract: A semiconductor package according to an exemplary embodiment of the present disclosure may comprise a semiconductor chip comprising a chip pad; a redistribution layer electrically connected to the chip pad of the semiconductor chip; an external connection terminal electrically connected to the redistribution layer; a sealing material covering the semiconductor chip and configured to fix the semiconductor chip and the redistribution layer; an adhesive film positioned on the upper surface of the sealing material; and a heat sink formed on the upper surface of the adhesive film and having a stepped portion at the periphery thereof.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 2, 2022
    Assignee: NEPES CO., LTD.
    Inventors: Nam Chul Kim, Jong Heon Kim, Eung Ju Lee, Yong Woon Yeo, Chang Woo Lee
  • Patent number: 11404680
    Abstract: A pixel bank manufacturing method, a pixel bank structure, a pixel structure, and a display panel are provided. The method includes providing a base substrate, wherein a plurality of anode thin film layers are manufactured on the base substrate; coating a photoresist layer used for covering the plurality of anode thin film layers on the base substrate; performing a photolithography on the photoresist layer by an exposing patterning structure, and baking to cure a remained photoresist layer after the photolithography to form a first bank layer; the exposing patterning structure is a structure that full via holes, first half via holes, a plurality of blind via holes, and second half via holes are arranged repeatedly; forming a second bank layer on the first bank layer; the second bank layer is a black bank layer.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 2, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoling Wu
  • Patent number: 11404492
    Abstract: A display device is provided. The display device includes: a display substrate on which a plurality of light-emitting areas are defined; and a color conversion substrate on which a plurality of light-transmitting areas respectively associated with the plurality of light-emitting areas and light-blocking areas between the plurality of light-transmitting areas are defined, the color conversion substrate comprising color patterns in the light-blocking areas, and light-blocking members on the color patterns, wherein at least one of the light-emitting areas has an area smaller than the area of the light-transmitting area that overlaps it in a thickness direction, and the color patterns include a blue colorant.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Bae Song, Shin Moon Kang, Da Hye Kim, Man Gi Kim, Sang Joon Ryu, Seung In Baek, Dae Woo Lee, Yeon Sung Lee, Youn Ho Han
  • Patent number: 11404562
    Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Ashish Agrawal, Benjamin Chu-Kung, Uygar E. Avci, Jack T. Kavalieros, Ian A. Young
  • Patent number: 11398616
    Abstract: An organic light-emitting display panel and a manufacturing method thereof are provided. A thin-film encapsulation layer in the organic light-emitting panel extends to cover a wall surface of the functional structure layer facing to a light-transmitting hole, and comprehensively protects the functional structure layer and the light-emitting layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 26, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Qi Ouyang, Mugyeom Kim, Yong Zhao