Patents Examined by Fernando L. Toledo
  • Patent number: 10707251
    Abstract: An array substrate for a digital X-ray detector and the digital X-ray detector including the same are disclosed. The array substrate effectively protects a PIN diode from external moisture or water, maximizes a light transmission region of a PIN diode, and reduces resistance by maximizing the region of a bias wiring. To this end, a closed-loop bias electrode formed to cover a circumferential surface of a PIN diode is used. In detail, the bias electrode includes a closed loop portion and a contact extension portion. The contact extension portion extends from one end of the closed loop portion so as to directly contact an upper electrode, and includes a hollow part therein.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Hanseok Lee, Hyungil Na, Jungjune Kim, Seungyong Jung
  • Patent number: 10707167
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 10707257
    Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Yu-Te Hsieh
  • Patent number: 10692845
    Abstract: A method for arraying micro-LED chips is disclosed. The method includes preparing a chip carrier formed with a plurality of chip pockets whose internal pressure is reduced through a plurality of suction holes, capturing the micro-LED chips in the corresponding chip pockets such that the micro-LED chips are in close contact with the bottoms of the chip pockets, and placing the micro-LED chips captured in the chip pockets on a base body. Each of the chip pockets includes a slope through which an inlet having a larger width than the bottom is connected to the bottom. The distances between the centers of the adjacent micro-LED chips placed on the base body are the same as those between the centers of the corresponding chip pockets.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: June 23, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Taekyung Yoo, Juok Seo, Bogyun Kim, Gunha Kim, Jugyeong Mun
  • Patent number: 10680139
    Abstract: An optical device package comprising a receptacle, an optical device received therein, and a window member disposed forward of the receptacle in a light emitting direction of the optical device. The window member is a member of synthetic quartz glass having front and back surfaces, at least one of the front and back surfaces being a rough surface.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 9, 2020
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Shuhei Ueda, Masaki Takeuchi, Harunobu Matsui
  • Patent number: 10680095
    Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A trench is defined within the semiconductor layer, the trench having an opening, a sidewall and a base. A pillar is provided below the trench and has a second conductivity type that is different than the first conductivity type. A metal layer is provided over the sidewall of the trench, the metal layer contacting the semiconductor layer at the sidewall of the trench to form a Schottky interface of a Schottky diode. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: June 9, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Wonhwa Lee, Gary H. Loechelt
  • Patent number: 10680079
    Abstract: A semiconductor structure and a method for fabricating the semiconductor structure are provided. The method includes forming a gate structure on a base substrate and forming a first dielectric layer on the base substrate. The first dielectric layer has a top lower than the gate structure and exposes a sidewall portion of the gate structure. The method also includes forming an isolation sidewall spacer on the exposed sidewall portion of the gate structure.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 9, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10672667
    Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10669634
    Abstract: A display apparatus includes a substrate on which a central area and a peripheral area adjacent to the central area are arranged. The central area includes a display area. The display apparatus further includes: at least one insulation pattern that is formed in the peripheral area; a groove from which a material for forming the insulation pattern is removed and that is formed adjacent to the insulation pattern; and at least one insulating layer that is interposed between the insulation pattern and the substrate. The groove is located in the at least one insulating layer.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: June 2, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sun-Youl Lee
  • Patent number: 10672749
    Abstract: A light source includes a plurality of semiconductor components, wherein a semiconductor component includes a plurality of light-emitting diodes, the diodes are arranged in a predefined grid in at least one column in or on the semiconductor component, and a control circuit that drives the individual diodes is arranged on the semiconductor component.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 2, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Matthias Goldbach, Juergen Holz, Stefan Illek, Stefan Groetsch
  • Patent number: 10665697
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 10665812
    Abstract: There is provided an organic EL display panel having a substrate, a plurality of pixel electrodes arranged in a matrix pattern on the substrate, and a light-emitting layer formed on each pixel electrode. The organic EL display panel includes a power supply auxiliary electrode layer securing an electrode forming region which extends in a row direction or a column direction on at least one of gaps between pixel electrodes adjoining to each other on the substrate in the row or column direction and being formed so as not to come into contact with the pixel electrode adjoining to the electrode forming region, a functional layer configured to be formed so as to extend over the light-emitting layer and the power supply auxiliary electrode layer, and a common electrode layer configured to be formed so as to continuously extend on the functional layer.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: May 26, 2020
    Assignee: JOLED INC.
    Inventors: Hiroyuki Ajiki, Masaki Nishimura
  • Patent number: 10665453
    Abstract: An object is to provide a high reliable semiconductor device including a thin film transistor having stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which an oxide semiconductor film is used for a semiconductor layer including a channel formation region, heat treatment (which is for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor film and reduce impurities such as moisture. Besides impurities such as moisture existing in the oxide semiconductor film, heat treatment causes reduction of impurities such as moisture existing in the gate insulating layer and those in interfaces between the oxide semiconductor film and films which are provided over and below the oxide semiconductor film and are in contact with the oxide semiconductor film.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: May 26, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Junichiro Sakata, Hiroki Ohara, Shunpei Yamazaki
  • Patent number: 10658628
    Abstract: An organic light emitting display device includes a substrate. A buffer layer is disposed on the substrate. The buffer layer includes a first opening exposing an upper surface of the substrate in a bending region. Pixel structures are positioned in a pixel region on the buffer layer. A fan-out wiring is positioned in the peripheral region and the pad region on the insulation layer structure such that the upper surface of the substrate and the first portion of the buffer layer are exposed. A passivation layer is disposed on the fan-out wiring, side walls of the insulation layer structure adjacent to the bending region, and the first portion of the buffer layer. The passivation layer includes a third opening exposing the upper surface of the substrate in the bending region. A connection electrode is positioned in the bending region on the substrate.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeongho Lee, Yanghee Kim, Juncheol Shin, Hokyoon Kwon, Deukjong Kim, Keunsoo Lee
  • Patent number: 10658359
    Abstract: A semiconductor device, which is a diode, includes the following: an n cathode layer, which is an n-type region, disposed in a surface layer of a semiconductor substrate; a p cathode layer, which is a p-type region, disposed in the surface layer; and a cathode electrode, which is a metal electrode, in contact with both of the n cathode layer and the p cathode layer. The cathode electrode includes a first metal layer in contact with both of the n cathode layer and the p cathode layer, and a second metal layer disposed on the first metal layer. A contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than the oxygen concentration of a contact surface between the first metal layer, and the n cathode layer and the p cathode layer.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Koji Tanaka, Fumihito Masuoka
  • Patent number: 10658286
    Abstract: A capacitor cell for a semiconductor device, wherein the capacitor cell comprises: a capacitor having a first node and a second node; a first electrode structure, comprising a first contact point and a second contact point, wherein the first contact point and the second contact point are electrically connected to the first node of said capacitor and located at two different edges of the capacitor cell; and a second electrode structure, comprising a third contact point and a fourth contact point, wherein the third contact point and the fourth contact point are electrically connected to the second node of said capacitor and located at said two different edges of the capacitor cell.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: May 19, 2020
    Assignee: Nuvoton Technology Corporation
    Inventors: Fu-Sheng Hsu, Ming-Chun Liang
  • Patent number: 10658439
    Abstract: Disclosed is a display device possessing: a substrate having a display region and a peripheral region surrounding the display region; a pixel over the display region; a passivation film over the pixel; a resin layer over the passivation film; a first dam over the peripheral region and surrounding the display region; and a second dam surrounding the first dam. The passivation film includes; a first layer containing an inorganic compound; a second layer over the first layer, the second layer containing an organic compound; and a third layer over the second layer, the third layer containing an inorganic compound. The second layer is selectively arranged in a region surrounded by the first dam. The resin layer is selectively arranged in a region surrounded by the second dam.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Japan Display Inc.
    Inventor: Jun Hanari
  • Patent number: 10658474
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 10648070
    Abstract: The present disclosure provides a mask assembly and a method for manufacturing the same, and a display device. The mask assembly includes a frame, a first mask and a second mask, and the first mask and the second mask are superposed on the frame; the first mask includes an opening region, the second mask includes an evaporation region in which a first evaporation hole is provided for allowing an evaporation material to pass therethrough and a buffer region surrounding the evaporation region and configured to block off the evaporation material, and an orthographic projection of the boundary of the opening region onto the second mask is located within the buffer region.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 12, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Dongwei Li, Baojun Li, Chun Chieh Huang
  • Patent number: 10651157
    Abstract: A semiconductor device includes a first substrate, a through substrate via, a second substrate, and a bonding structure. The first substrate includes a first dielectric material, and the first dielectric material includes a first conductive pad embedded therein. The through substrate via is formed in the first substrate. The second substrate includes a second dielectric material, the second dielectric material includes a second conductive pad embedded therein, the first dielectric material is different from the second dielectric material, the second conductive pad has a first height, the second dielectric material has a second height, and the first height is less than the second height. The bonding structure is formed between the first substrate and the second substrate, wherein the bonding structure includes the first conductive pad bonded to the second conductive pad and the first dielectric material bonded to the second dielectric material.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: May 12, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su