Abstract: A method of packaging a semiconductor includes: positioning first and second semiconductor dies by one another on a carrier substrate, wherein first and second zones zone are defined with respect to the first die and third and fourth zones are defined with respect to the second die; forming first vias in the first zone, the first vias having a first size; forming second vias in the second zone, the second vias having a second size different from the first; forming third vias in the third zone, the third vias having a third size; forming fourth vias in the fourth zone, the fourth vias having a fourth size different from the third; and electrically connecting the first and second dies with an interconnection die such that electrical signals are exchangeable therebetween.

Abstract: A passive amplifier is provided that includes an input sampling switch, a sampling capacitance, and metal-oxide-semiconductor capacitor devices. An input signal may be sampled onto the sampling capacitance by turning on the input sampling switch while the metal-oxide-semiconductor capacitors are activated. After the sampling phase, the metal-oxide-semiconductor capacitors are deactivated to provide a voltage gain. The voltage gain can be conditionally applied depending on the signal level of the sampled input.

Abstract: A pixel that emits light at brightness corresponding to the amount of a driving current regardless of a threshold voltage of a driving transistor, and secure sufficient compensation time by separating an operation of compensating for the threshold voltage of the driving transistor and an operation of writing a data signal, and a display apparatus including the pixel.

Abstract: A memory device includes a first bit cell, a second bit cell, a first word line and a second word line. A first boundary of the second bit cell is adjacent with a first boundary of the first bit cell. The first word line is coupled to the first bit cell. The second word line is coupled to the second bit cell. A first segment of the first word line is overlapped with the first boundary of the second bit cell in a plan view, and a first segment of the second word line is overlapped with a second boundary of the second bit cell in the plan view.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, bit lines, and word lines. The capacitor structure is arranged on the substrate, the transistor structure is arranged on a side of the capacitor structure, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word lines, and other one of the source and the drain of the transistor structure is electrically connected to the bit lines. A word line isolation structure is arranged between adjacent two of the word lines, and a bit line isolation structure is arranged between adjacent two of the bit lines. A width of the word line isolation structure is not equal to a width of the bit line isolation structure.

Abstract: A field effect transistor may include an active layer containing an oxide compound material of at least two atomic elements including a first element of tin and a second element selected from Ge, Si, P, S, F, Ti, Cs, and Na and located over a substrate. The field effect transistor may further include a gate dielectric located on the active layer, a gate electrode located on the gate dielectric, and a source contact structure and a drain contact structure contacting a respective portion of the active layer. The oxide compound material may include at least germanium and tin. The oxide compound semiconductor material may be used as a p-type semiconductor material in BEOL structures.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

Abstract: Disclosed is a method of forming a chalcogenide-based thin film using an atomic layer deposition (ALD) process including forming a Ge—Te-based material, the forming of the Ge—Te-based material may include a first operation of supplying, into a reaction chamber provided with a substrate, a first source gas including a Ge precursor with Ge having an oxidation state of +2, a second operation of supplying a first purge gas into the reaction chamber, a third operation of supplying, into the reaction chamber, a second source gas including a Te precursor and a first co-reactant gas for promoting a reaction between the Ge precursor and the Te precursor, and a fourth operation of supplying a second purge gas into the reaction chamber.

Abstract: The present disclosure provides a display panel, having a light emitting layer, a transparent spacing layer on the light emitting layer, and a wavelength converting layer on the transparent spacing layer, wherein according to the luminance change ratios of the wavelength converting units of adjacent pixels and the light path property of the transparent spacing layer, the cross color issue in wavelength-conversion type display panels is at least partially solved by controlling the intensity proportions of the light arriving at the wavelength converting units of adjacent sub-pixels within a certain range.

Abstract: A display apparatus having a light detection function is provided. The display apparatus includes a first pixel and a second pixel. The first pixel includes a first subpixel and a second subpixel. The second pixel includes a third subpixel. The first subpixel is a subpixel that emits light with the shortest wavelength (e.g., blue light or light with a shorter wavelength than blue light) in subpixels included in the first pixel. The second subpixel has a function of receiving the light emitted by the first subpixel. The third subpixel is a subpixel that emits light with the shortest wavelength in subpixels included in the second pixel. The wavelength of the light emitted by the first subpixel is shorter than the wavelength of the light emitted by the third subpixel.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A first conductive feature is over the substrate. A second conductive feature is over the substrate and is adjacent to the first conductive feature. The first and second conductive features are separated by a cavity. A dielectric liner extends from the first conductive feature to the second conductive feature along a bottom of the cavity and further extends along opposing sidewalls of the first and second conductive features. A dielectric cap covers and seals the cavity. The dielectric cap has a top surface that is approximately planar with top surfaces of the first and second conductive features. The first conductive feature and the second conductive feature comprise graphene intercalated with one or more metals.

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming a first trench in a substrate, disposing a first gate electrode in the first trench, and disposing a dummy gate electrode on the first gate electrode in the first trench. The method also includes removing the dummy gate electrode from the first gate electrode and forming a first doped region in the first gate electrode.

Abstract: An integrated circuit (IC) package substrate, comprising a magnetic material embedded within a dielectric material. A first surface of the dielectric material is below the magnetic material, and a second surface of the dielectric material, opposite the first surface, is over the magnetic material. A metallization level comprising a first metal feature is embedded within the magnetic material. A second metal feature is at an interface of the magnetic material and the dielectric material. The second metal feature has a first sidewall in contact with the dielectric material and a second sidewall in contact with the magnetic material.

Abstract: A one-time programmable nonvolatile memory cell includes a substrate providing a first conductivity type well and a second conductivity type well, a first MOS transistor having a floating gate and a gate oxide, and an auxiliary gate and a gate oxide formed by extending one end of the floating gate and the gate oxide of the first MOS transistor from an edge of the first active region, along a second direction perpendicular to the first direction, passing through the isolation region until to cover a part or an entire of the second active region. The first and the second active regions are separated by an isolation region, and the first and second active regions and the isolation region are arranged parallel to each other along a first direction. The memory cell has an improved structure and optimized performance and a reduced size.

Abstract: A magnetoresistance memory device includes first, second, third and fourth ferromagnetic layers; a first and second ferromagnetic oxide layers; a metal layer; an insulating layer. The second ferromagnetic layer includes one of iron and cobalt included in the first ferromagnetic oxide layer and one element of a first element group. The second ferromagnetic oxide layer includes an oxide of an alloy of the one of iron and cobalt included in the second ferromagnetic oxide layer with a first element, which has a standard electrode potential lower than that of iron or cobalt and that of the one element of the first element group included in the second ferromagnetic layer.

Abstract: An electronic device includes an insulating base including a strip-shaped portion having elasticity and an island-shaped portion connected to the strip-shaped portion, an organic insulating film disposed on the insulating base, an inorganic insulating film disposed on the organic insulating film, a wiring disposed between the strip-shaped portion and the organic insulating film, an electrical element disposed on the inorganic insulating film and electrically connected to the wiring, in the island-shaped portion, a barrier wall overlapping the island-shaped portion and the strip-shaped portion and surrounding the electrical element, and a sealing film covering the electrical element.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.

Abstract: In one aspect of the present disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes a first conductive structure extending in a first direction, the first conductive structure coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed over, in a third direction perpendicular to the first direction and the second direction, the first conductive structure; and a via structure disposed over the second conductive structure and in contact with the dielectric material, wherein the dielectric material is configured to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The method includes: forming a first bottom isolation layer and a second bottom isolation layer in a substrate, the thickness of the second bottom isolation layer being less than that of the first bottom isolation layer; and forming, on the a first active area in the substrate, a first gate structure extending to the first bottom isolation layer and forming, on a second active area in the substrate, a second gate structure extending to the second bottom isolation layer.

Abstract: A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.