Abstract: A planar sensor array, like an imaging sensor array, can be mounted to a ceramic circuit board to provide improved mechanical stability and heat dissipation. Embodiments herein provide improvements to such assemblies by providing two or more recesses in the ceramic circuit board opposite the sensor array. Electronic components can be placed in these recesses, reducing the overall size and moment of inertia of the sensor assembly relative to placement on the same side of the ceramic circuit board as the sensor array. Placing the electronics in the two or more recesses allows for simplified mounting of the assembly to heat sinks, flexible circuit boards, or other elements. The two or more recesses are separated by a stiffening cross-brace portion of the ceramic circuit board that enhances the mechanical strength of the ceramic circuit board.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a radiating element structure and a semiconductor die. The radiating element structure includes a non-conductive substrate, a radiating element formed at a top side of the non-conductive substrate, and a conductive ring formed at the top side of the non-conductive substrate substantially surrounding the radiating element. The semiconductor die is interconnected with the radiating element by way of a conductive trace. An encapsulant encapsulates at least a portion of the radiating element structure. A top surface of the conductive ring exposed at a top surface of the encapsulant. A waveguide interface material is applied on at least a portion of the top surface of the encapsulant.

Abstract: An electronic device includes a carrier substrate having a front face and an electronic chip mounted on the front face. An encapsulation cover is mounted above the front face and bounds a chamber in which the chip is situated. A front opening is provided in front of an optical component of the chip. An optical element, designed to allow light to pass, is mounted on the cover in a position which covers the front opening of the cover. The optical element includes a central region designed to deviate light and a positioning pattern that is visible through the front opening. An additional mask is mounted on the encapsulation cover in a position which extends in front of the optical element. A local opening of the additional mask is situated in front of the optical component.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels including a light emitting element and a pixel circuit, the light emitting element includes a second electrode including a main body electrode. The sub-pixels include a first color sub-pixel which includes a first connecting portion. In the first color sub-pixel, the connecting electrode is connected with the first connecting portion through a first via hole, and the first connecting portion is electrically connected with the pixel circuit through a first connecting hole; and the first via hole and the first connecting hole are not overlapped with the main body electrode, and orthographic projections of the first via hole and the first connection hole on a first straight line extending in an extension direction of the data line are overlapped.

Abstract: An organic light emitting diode display includes a lower substrate, a sub-pixel structure, an upper substrate, a sealant, and a first power supply wire. The lower substrate has a display area, a peripheral area, and a pad area. The sub-pixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The first power supply wire is disposed between the lower substrate and the sealant, and overlaps the lower substrate and the sealant. The first power supply wire includes a first protrusion protruding in a first direction that is a direction from the pad area to the display area in the first peripheral area.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: Packaged semiconductor devices including heat-dissipating structures and methods of forming the same are disclosed. In an embodiment, a semiconductor package includes a semiconductor die including a substrate, a front-side interconnect structure on a front-side of the substrate, and a backside interconnect structure on a backside of the substrate opposite the front-side interconnect structure; a support die disposed on the front-side interconnect structure; a heat-dissipating structure on the support die, the heat-dissipating structure being thermally coupled to the semiconductor die and the support die; a redistribution structure on the backside interconnect structure opposite the substrate, the redistribution structure being electrically coupled to the semiconductor die; and an encapsulant on the redistribution structure and adjacent to side surfaces of the semiconductor die, the support die, and the heat-dissipating structure.

Abstract: Compositions comprising a) one or more amorphous superconductor layers bound to one or more flexible substrate layers, or b) one or more superconductor layers bound to one or more layers of a high dielectric material are disclosed. Furthermore, provided herein are articles comprising one or more compositions of the invention and method of manufacturing thereof.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate provided with a drift region; a buffer region arranged between the drift region and the lower surface, wherein a doping concentration distribution has three or more concentration peaks; and a collector region arranged between the buffer region and the lower surface, wherein the three or more concentration peaks in the buffer region include: a first concentration peak closest to the lower surface; a second concentration peak closest, next to the first concentration peak, to the lower surface, arranged 5 ?m or more distant from the lower surface in the depth direction, and having a doping concentration lower than the first concentration peak, the doping concentration being less than 1.0×1015/cm3; and a high concentration peak arranged farther from the lower surface than the second concentration peak, and having a higher doping concentration than the second concentration peak.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method includes providing a substrate including an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: GaN vertical trench MOSFETs and methods of manufacturing the same are disclosed. One example embodiment is a vertical trench MOSFET. The MOSFET includes a semiconductor transistor that has a first surface and a second surface, and a trench that extends from the first surface into the semiconductor transistor along a first direction perpendicular to the first and second surfaces. The semiconductor transistor includes a body region having a channel region arranged along the first direction along at least a portion of a wall of the trench. The doping concentration of the channel region is non-uniform. As a non-limiting example, two-step doping is conducted for forming asymmetric or non-uniform channel of a GaN vertical trench MOSFET. In some embodiments, multiple-step doping other than the two-step doing (such as doping in three steps, four steps, or more), linearly scaled doping, other proper asymmetric doping can be used.

Abstract: Disclosed herein are devices, systems, and methods can improve the signal-to-noise ratio of measurements made in biological applications. In some embodiments, an amplifier circuit that comprises a three-terminal device is situated in a configuration (e.g., a common-base or similar configuration) that allows the circuit to detect current through a nanopore while providing feedback to the sense electrode to reduce parasitic capacitance between the sense electrode and the counter electrode. The amplifier circuit may include, for example, a bi-polar junction transistor (BJT), a diamond transistor, a CMOS transistor, an operational transconductance amplifier, a voltage-controlled current source, a transconductor, a macro transistor, and/or a second-generation current conveyor (CCII+).

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes the following operations. A semiconductor substrate is provided, the semiconductor substrate includes multiple bit line structures disposed at intervals along a first direction; for each of the multiple bit line structures, surfaces of the bit line structure are filled with a conductive material to form a conductive layer covering the surfaces of the bit line structure. A top surface of the conductive layer is higher than a top surface of the bit line structure; and the conductive layer is etched to form multiple first conductive layers independent of each other and multiple second conductive layers, each of which is located on a respective one of the first conductive layers.

Abstract: A device includes a plurality of magnetic random-access memory (MRAM) cells in a first region of the device; and a dummy MRAM pillar disposed in a second region of the device, wherein the dummy MRAM pillar is not connected to an active metal feature.

Abstract: A semiconductor light emitting element includes: a substrate; an n-type layer; a light emitting layer; a p-type layer; a p electrode located above the p-type layer; an n electrode located in a region that is above the n-type layer and in which the light emitting layer and the p-type layer are not located; a p-electrode bump connected to the p electrode; an n-electrode bump connected to the n electrode; and an insulation bump located in at least one of a region between the n-electrode bump and the p-type layer and a region whose distance from an end of the p-type layer closer to the n-electrode bump is shorter than a distance from the end to the p-electrode bump, in a plan view of the substrate. A surface of the insulation bump opposite to a surface facing the substrate is insulated from the p electrode and the n electrode.

Abstract: Provided is a nanowire array, in which a plurality of nanowires are densely packed and in contact with each other via side walls to form a three-dimensional, compact layer structure, wherein the plurality of nanowires are formed from InGaN-based material. Also provided is an optoelectronic device comprising the nanowire array which is epitaxially grown on a surface of a substrate (12). Further provided are methods for preparing the nanowire array and the optoelectronic device.

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

Abstract: The present disclosure provides a method of forming a semiconductor structure. The method comprises providing a substrate comprising an isolation region, an active region adjacent to the isolation region, and a first top surface, wherein the isolation region includes an isolation trench filled with a dielectric material, and the active region includes a gate trench filled with a gate electrode material; forming a hard mask on the substrate; and performing an etching process to partially remove portions of the dielectric material and gate electrode material exposed by the hard mask to form a second top surface of the dielectric material and a third top surface of the gate electrode material, wherein the second top surface and the third top surface are substantially at the same level and are substantially lower than the first top surface.

Abstract: A semiconductor includes a gate structure on a substrate and including a gate electrode, a source/drain pattern on a side surface of the gate electrode, a source/drain contact connected to the source/drain pattern, a first etching stop film structure on the source/drain contact and the gate structure, the first etching stop film structure including a first lower etching stop film and a silicon nitride film on the first lower etching stop film, and a first via plug inside the first etching stop film structure and connected to the source/drain contact, wherein the first lower etching stop film includes aluminum, and wherein an upper surface of the silicon nitride film is on a same plane as an upper surface of the first via plug.