Patents Examined by Fernando L. Toledo
  • Patent number: 11908865
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The semiconductor structure includes a substrate. The substrate includes a first region, a second region, and an isolation region between the first region and the second region. The semiconductor structure also includes a first fin, a second fin and a third fin disposed over the first region, the second region, and the isolation region, respectively. Further, the semiconductor structure includes a gate structure. The gate structure includes a first work function layer over the first region and a first portion of the isolation region, and a second work function layer over the second region and a second portion of the isolation region. An interface where the first work function layer is in contact with the second work function layer is located over a top surface of the third fin.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: February 20, 2024
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Da Huang, Yao Qi Dong, Xiaowan Dai, Zhen Tian
  • Patent number: 11908861
    Abstract: A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Munhyeon Kim, Mingyu Kim, Doyoung Choi, Daewon Ha
  • Patent number: 11908863
    Abstract: A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 20, 2024
    Assignee: UNIST(ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Kyung Rok Kim, Jae Won Jeong, Young Eun Choi, Woo Seok Kim, Jiwon Chang
  • Patent number: 11908906
    Abstract: A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 20, 2024
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Hailong Yu, Xuezhen Jing, Hao Zhang, Tiantian Zhang, Jinhui Meng
  • Patent number: 11908921
    Abstract: The present disclosure is directed to method for the fabrication of spacer structures between source/drain (S/D) epitaxial structures and metal gate structures in nanostructure transistors. The method includes forming a fin structure with alternating first and second nanostructure elements on a substrate. The method also includes etching edge portions of the first nanostructure elements in the fin structure to form cavities. Further, depositing a spacer material on the fin structure to fill the cavities and removing a portion of the spacer material in the cavities to form an opening in the spacer material. In addition, the method includes forming S/D epitaxial structures on the substrate to abut the fin structure and the spacer material so that sidewall portions of the S/D epitaxial structures seal the opening in the spacer material to form an air gap in the spacer material.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: February 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Yun Peng, Fu-Ting Yen, Keng-Chu Lin
  • Patent number: 11908751
    Abstract: In an embodiment, a method includes: etching a trench in a substrate; depositing a liner material in the trench with an atomic layer deposition process; depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process; converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material; and forming a hybrid fin in the portion of the trench unfilled by the solid insulation material.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Ying Chen, Sen-Hong Syue, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11901412
    Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winne Victoria Wei-Ning Chen, Pang-Yen Tsai
  • Patent number: 11901440
    Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 13, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Christopher J. Waskiewicz, Su Chen Fan, Brent Anderson, Junli Wang
  • Patent number: 11894243
    Abstract: A wafer system-level fan-out packaging structure and a manufacturing method. The method includes: forming a redistribution layer, where the redistribution layer includes a first surface and an opposite second surface; providing a patch element, and bonding the patch element to the second surface; providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer through the bump; and forming a plastic packaging layer on the second surface of the redistribution layer, where the plastic packaging layer covers the patch element, back side and side surfaces of the die. In the wafer system-level fan-out packaging structure and the manufacturing method of the present disclosure, the die and the patch element are packaged in a plastic packaging layer, and the die and the patch element are connected and let out by the redistribution layer.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 6, 2024
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengchung Lin
  • Patent number: 11894310
    Abstract: A fan-out semiconductor package including a first redistribution layer; a first semiconductor chip on the first redistribution layer; an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip; a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and a second redistribution layer on the molded layer, wherein the interconnector includes a metal ball and is electrically connected to the first redistribution layer, the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring, the first via is connected to the interconnector, and a part of the first via is in the molded layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Sam Kang, Ki Ju Lee, Young Chan Ko, Jeong Seok Kim, Bong Ju Cho
  • Patent number: 11869839
    Abstract: A packaged electronic device includes a semiconductor die with an electronic component and a contact structure connected to the electronic component, as well as an organic panel frame, a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame, and a ceramic substrate mounted to a first side of the semiconductor die.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Woochan Kim, Benjamin Allen Samples, Vivek Kishorechand Arora
  • Patent number: 11869966
    Abstract: A method includes forming a trench in a first surface in an edge region of a semiconductor body, forming a plurality of superjunction transistor cells in an inner region of a semiconductor body, and forming an insulation layer on the first surface of the semiconductor body in the edge region and in the inner region, wherein forming the insulation layer includes a thermal oxidation process.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: January 9, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Hans Weber, Christian Fachmann, Franz Hirler, Winfried Kaindl, Markus Rochel
  • Patent number: 11862657
    Abstract: To achieve a size reduction of a semiconductor package while securing stability in mounting. Three terminals t1, t2, and t4 are individually arranged on a semiconductor package 10 having a rectangular shape as viewed in plan in such a manner that the center in the longitudinal direction of the semiconductor package 10 of each of the three terminals t1, t2, and t4 and the center in the longitudinal direction of each of the other terminals are not overlapped with each other as viewed from the side of the long side.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: January 2, 2024
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Osamu Shirata, Yusuke Hidaka
  • Patent number: 11854989
    Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: December 26, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongho Kim, Jongbo Shim, Hwan Pil Park, Choongbin Yim, Jungwoo Kim
  • Patent number: 11855159
    Abstract: Various embodiments of the present application are directed to a method for forming a thin semiconductor-on-insulator (SOI) substrate without implantation radiation and/or plasma damage. In some embodiments, a device layer is epitaxially formed on a sacrificial substrate and an insulator layer is formed on the device layer. The insulator layer may, for example, be formed with a net charge that is negative or neutral. The sacrificial substrate is bonded to a handle substrate, such that the device layer and the insulator layer are between the sacrificial and handle substrates. The sacrificial substrate is removed, and the device layer is cyclically thinned until the device layer has a target thickness. Each thinning cycle comprises oxidizing a portion of the device layer and removing oxide resulting from the oxidizing.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Ta Wu, Chia-Shiung Tsai, Jiech-Fun Lu, Kuo-Hwa Tzeng, Shih-Pei Chou, Yu-Hung Cheng, Yeur-Luen Tu
  • Patent number: 11855191
    Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: December 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brent Anderson, Junli Wang, Indira Seshadri, Chen Zhang, Ruilong Xie, Joshua M. Rubin, Hemanth Jagannathan
  • Patent number: 11849614
    Abstract: An organic light emitting diode display includes a lower substrate, a sub-pixel structure, an upper substrate, a sealant, and a first power supply wire. The lower substrate has a display area, a peripheral area, and a pad area. The sub-pixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the sub-pixel structure. The sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The first power supply wire is disposed between the lower substrate and the sealant, and overlaps the lower substrate and the sealant. The first power supply wire includes a first protrusion protruding in a first direction that is a direction from the pad area to the display area in the first peripheral area.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Bongwon Lee, Yanghee Kim, Hyun-Chol Bang, Sujin Lee
  • Patent number: 11848205
    Abstract: A semiconductor structure and a manufacturing method therefor are provided by embodiments of the present application. A buffer layer is disposed on a substrate layer, and the buffer layer includes a first buffer layer and a second buffer layer. By doping a transition metal in the first buffer layer, a deep level trap may be formed to capture background electrons, and diffusion of free electrons toward the substrate may also be avoided. In the second buffer layer, by decreasing a doping concentration of the transition metal or not doping intentionally the transition metal, a tailing effect is avoided and current collapse is prevented. By doping periodically C in the buffer layer, C may be as an acceptor impurity to compensate the background electrons, and then a concentration of the background electrons is reduced.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: December 19, 2023
    Assignee: ENKRIS SEMICONDUCTOR, INC.
    Inventors: Kai Cheng, Kai Liu
  • Patent number: 11848233
    Abstract: A method includes the following steps. A seed layer is formed over a structure having at least one semiconductor die. A first patterned photoresist layer is formed over the seed layer, wherein the first patterned photoresist layer includes a first opening exposing a portion of the seed layer. A metallic wiring is formed in the first opening and on the exposed portion of the seed layer. A second patterned photoresist layer is formed on the first patterned photoresist layer and covers the metallic wiring, wherein the second patterned photoresist layer includes a second opening exposing a portion of the metallic wiring. A conductive via is formed in the second opening and on the exposed portion of the metallic wiring. The first patterned photoresist layer and the second patterned photoresist layer are removed. The metallic wiring and the conductive via are laterally wrapped around with an encapsulant.
    Type: Grant
    Filed: March 27, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yuan Teng, Bor-Rung Su, De-Yuan Lu, Hao-Yi Tsai, Tin-Hao Kuo, Tzung-Hui Lee, Tai-Min Chang
  • Patent number: 11837533
    Abstract: A semiconductor package including: a first substrate including a first surface including a first region and a second region at least partially surrounding the first region, wherein the first substrate includes a first insulating layer, a first conductive pattern in the first insulating layer, a first passivation layer disposed in the first region and the second region, and a second passivation layer disposed on the first passivation layer in the second region; an interposer overlapping the first substrate and including a second insulating layer and a second conductive pattern in the second insulating layer; a first connection terminal disposed on the first passivation layer in the first region; and a second connection terminal disposed on the second passivation layer in the second region, wherein the first conductive pattern and the second conductive pattern are connected to each other through the first connection terminal and the second connection terminal.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong Ho Kim, Jang Woo Lee