Patents Examined by Fernando L. Toledo
  • Patent number: 10957549
    Abstract: A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Guangjun Yang
  • Patent number: 10950782
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a nitride diffusion barrier (NDB) has a L2/L1/NL or NL/L1/L2 configuration wherein NL is a metal nitride or metal oxynitride layer, L2 blocks oxygen diffusion from an adjoining Hk enhancing layer, and L1 prevents nitrogen diffusion from NL to the free layer (FL) thereby enhancing magnetoresistive ratio and FL thermal stability, and minimizing resistance x area product for the MTJ. NL is the uppermost layer in a bottom spin valve configuration, or is formed on a seed layer in a top spin valve configuration such that L2 and L1 are always between NL and the FL or pinned layer, respectively. In other embodiments, one or both of L1 and L2 are partially oxidized. Moreover, either L2 or L1 may be omitted when the other of L1 and L2 is partially oxidized. A spacer between the FL and L2 is optional.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: March 16, 2021
    Assignee: Headway Technologies, Inc.
    Inventors: Santiago Serrano Guisan, Luc Thomas, Jodi Mari Iwata, Guenole Jan, Vignesh Sundar
  • Patent number: 10943951
    Abstract: In one example embodiment, a SOT-MRAM includes a storage unit having a Co?X?Pt? based free layer. The storage unit includes a bottom electrode and the Co?X?Pt? based free layer is disposed over the bottom electrode. Further, the storage unit includes a tunnel barrier layer over the Co?X?Pt? based free layer, and a fixed layer over the tunnel barrier layer. The Co?X?Pt? based free layer, tunnel barrier layer and fixed layer form a magnetic tunnel junction. The storage unit may also include a top electrode over the MTJ.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 9, 2021
    Assignee: National University of Singapore
    Inventors: Jingsheng Chen, Jinyu Deng, Liang Liu
  • Patent number: 10943855
    Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: March 9, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Maria Cristina Estacio, Marlon Bartolo, Maria Clemens Ypil Quinones, Chung-Lin Wu
  • Patent number: 10943965
    Abstract: Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngjin Cho, Hyunwoong Kim, Joong-soo Moon, Seung-kyu Lee, Yangwan Kim
  • Patent number: 10942315
    Abstract: The back reflection in photodiodes is caused by an abrupt index contrast between the input waveguide and the composite waveguide/light absorbing material. In order to improve the back reflection, it is proposed to introduce an angle between the waveguide and the leading edge of the light absorbing material. The angle will result in gradually changing the effective index between the index of the waveguide and the index of the composite section, and consequently lower the amount of light reflecting back.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: March 9, 2021
    Assignee: Elenion Technologies, LLC
    Inventors: Saeed Fathololoumi, Yang Liu, Yaojia Chen
  • Patent number: 10937987
    Abstract: An electronic device may have a flexible organic light-emitting diode display layer. The edge of the flexible display layer may be bent. The display may have pixels formed from organic light-emitting diodes having anodes characterized by anode surface normals. For pixels in some regions of the display such as the bent edge of the display, the display may be characterized by a display surface normal for a pixel that differs from an anode surface normal for the anode of the organic light-emitting diode of that pixel. By tilting the anodes in this way, color shifts due to off-axis viewing of the pixels in the bend edge of the display can be minimized. If desired, tilted anodes may have multiple areas with different tilts. Sets of pixels with different anode tilts or other characteristics that differ may be supplied with common pixel data values.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 2, 2021
    Assignee: Apple Inc.
    Inventors: Jean-Pierre S. Guillou, Meng-Huan Ho, Ming Xu, Rui Liu, Shawn R. Gettemy, Yi Qiao
  • Patent number: 10937729
    Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: March 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-han Park
  • Patent number: 10937835
    Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: March 2, 2021
    Assignee: BAE Systems Imaging Solutions Inc.
    Inventor: Robert Daniel McGrath
  • Patent number: 10930689
    Abstract: A photoelectric conversion apparatus includes a semiconductor layer including a photoelectric conversion portion, a charge holding portion configured to hold electric charge generated from the photoelectric conversion portion, and a charge detection portion to which the electric charge held by the charge holding portion is transferred. A gate electrode of a transistor and a light shielding film including a first portion covering the charge holding portion and a second portion covering an upper surface of the gate electrode are disposed above the semiconductor layer. The distance between the second portion of the light shielding film and the upper surface of the gate electrode is greater than the distance between the first portion of the light shielding film and the semiconductor layer.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: February 23, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Toshiyuki Ogawa, Hajime Ikeda
  • Patent number: 10916587
    Abstract: An image sensor includes a first organic photoelectric conversion layer on a base layer, a floating diffusion region in the base layer, a first storage node including a first electrode layer, which is configured to receive a bias signal, a first portion of a first semiconductor layer which includes a semiconductor material, and a first portion of a first dielectric layer. The first dielectric layer extends between the first electrode layer and the first semiconductor layer. The first storage node is electrically connected to the first organic photoelectric conversion layer. The image sensor includes a first transfer transistor including the first dielectric layer, the first semiconductor layer, and a first transfer gate electrode which is configured to receive first transfer control signal. The first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 9, 2021
    Inventors: Tae Yon Lee, Chang Hwa Kim, Jae Ho Kim, Sang Chun Park, Gwi Deok Ryan Lee, Beom Suk Lee, Jae Kyu Lee, Kazunori Kakehi
  • Patent number: 10910428
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: February 2, 2021
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Patent number: 10910454
    Abstract: A display device includes a substrate, regions on the substrate each including a transparent first and a second regions, one or more light-emitting elements disposed in the second region, and a circular polarizing pattern disposed in front of the pixel regions. Each of the one or more light-emitting elements includes a reflective electrode and a transparent electrode layered one above the other, and a light-emitting film provided between the transparent electrode and the reflective electrode. The light-emitting film is configured to emit light in response to electric current supplied between the reflective electrode and the transparent electrode. The circular polarizing pattern covers the entire reflective electrode when seen from the front of the display device. At least a part of the first region is located within a gap in the circular polarizing pattern when seen from the front of the display device.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: February 2, 2021
    Assignees: TIANMA JAPAN, LTD., Wuhan Tianma Micro-Electronics Co., Ltd.
    Inventors: Kazushige Takechi, Hiroshi Tanabe
  • Patent number: 10903213
    Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: January 26, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sidharth Rastogi, Subhash Kuchanuri, Raheel Azmat, Pan-jae Park, Chul-hong Park, Jae-seok Yang, Kwan-young Chun
  • Patent number: 10903269
    Abstract: A magnetic memory device includes a first dielectric layer on a substrate, first and second via plugs in the first dielectric layer, first and second cylindrical memory stacks on the first and second via plugs, respectively, and an insulating cap layer conformally disposed on the first dielectric layer and on sidewalls of the first and second cylindrical memory stacks. The insulating cap layer is not disposed in a logic area and a via forming region between the first and second cylindrical memory stacks.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: January 26, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Wei Kuo, Yu-Tsung Lai, Jiunn-Hsiung Liao
  • Patent number: 10903233
    Abstract: A semiconductor device according to an embodiment includes first conductors, a second conductor, a first semiconductor, a multi-layered body, and a third conductor. The second conductor is provided above the first conductors. The multi-layered body is provided between the first semiconductor and the first conductors, and between the first semiconductor and the second conductor. The third conductor is provided between the multi-layered body and the second conductor. The first semiconductor includes a first portion facing an uppermost first conductor and a second portion facing the second conductor. The first semiconductor is continuous at least from the first portion to the second portion.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Nakaki
  • Patent number: 10903196
    Abstract: A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Sang Hyuk Lim
  • Patent number: 10903131
    Abstract: A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Jun Sung, Sungkyu Kim
  • Patent number: 10896946
    Abstract: An organic light emitting diode display device includes a substrate, light emitting structures, fan-out wirings, and a wiring structure. The substrate has a display region including a light emitting region and a peripheral region surrounding the light emitting region and a pad region located in one side of the display region. The light emitting structures are disposed in the light emitting region on the substrate. The fan-out wirings are disposed in the peripheral region on the substrate, and the fan-out wirings include a straight-line portion and an oblique line portion. The wiring structure is disposed on the fan-out wirings, and includes a conductive layer and conductive patterns spaced apart from each other and disposed on the conductive layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 19, 2021
    Inventors: Jisu Na, Kwang-Min Kim, Ki Wook Kim, Hyun Joon Kim
  • Patent number: 10897009
    Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Ravi Pillarisetty, Prashant Majhi, Uday Shah, Ryan E Arch, Markus Kuhn, Justin S. Brockman, Huiying Liu, Elijah V Karpov, Kaan Oguz, Brian S. Doyle, Robert S. Chau