Patents Examined by Fernando Toledo
  • Patent number: 9252161
    Abstract: Source wires having a semiconductor film thereunder are formed wide within a range that does not overlap pixel electrodes formed later. Thereafter, a resist pattern for use in patterning the pixel electrodes is formed so as to overlap edge portions of the source wires, and etching using the resist pattern as a mask is performed, whereby the pixel electrodes are formed, and in addition, the edge portions of the source wires are removed, whereby a structure in which the semiconductor film has a portion projecting beyond the source wires on both sides is formed.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: February 2, 2016
    Inventors: Toshihiko Iwasaka, Makoto Hirakawa
  • Patent number: 9252253
    Abstract: According to example embodiments, a high electron mobility transistor (HEMT) includes a channel layer having a 2-dimensional electron gas (2DEG), a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart from each other on one of the channel layer and the channel supply layer, at least one channel depletion layer on the channel supply layer; a gate electrode on at least a part of the channel depletion layer, and at least one bridge connecting the channel depletion layer and the source electrode. The channel depletion layer is configured to form a depletion region in the 2DEG. The HEMT has a ratio of a first impedance to a second impedance that is a uniform value. The first impedance is between the gate electrode and the channel depletion layer. The second impedance is between the source electrode and the channel depletion layer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: February 2, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: In-jun Hwang
  • Patent number: 9171762
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Zhao-Cheng Chen
  • Patent number: 9129943
    Abstract: An array includes a substrate having a frontside surface and a backside surface. A backside cavity is formed in the backside surface. Backside through vias extend through the substrate from the frontside surface to the backside surface. Embedded component through vias extend through the substrate from the frontside surface to the backside cavity. An embedded component is mounted within the backside cavity and coupled to the embedded component through vias. In this manner, the embedded component is embedded within the substrate.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: September 8, 2015
    Inventors: Ronald Patrick Huemoeller, Michael Kelly, David Jon Hiner
  • Patent number: 9012848
    Abstract: A laser-radiation sensor includes a copper substrate on which is grown an oriented polycrystalline buffer layer surmounted by an oriented polycrystalline sensor-element of an anisotropic transverse thermoelectric material. An absorber layer, thermally connected to the sensor-element, is heated by laser-radiation to be measured and communicates the heat to the sensor-element, causing a thermal gradient across the sensor-element. Spaced-apart electrodes in electrical contact with the sensor-element sense a voltage corresponding to the thermal gradient as a measure of the incident laser-radiation power.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: April 21, 2015
    Assignee: Coherent, Inc.
    Inventors: Robert Semerad, Erik Krous, James Schloss
  • Patent number: 8994054
    Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, a second electrode, a third electrode, and a fourth electrode. The stacked structural body includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The first electrode is electrically connected to the first semiconductor layer. The second electrode forms an ohmic contact with the second semiconductor layer. The second electrode is translucent to light emitted from the light emitting layer. The third electrode penetrates through the second electrode and is electrically connected to the second electrode to form Shottky contact with the second semiconductor layer. The third electrode is disposed between the fourth electrode and the second semiconductor layer.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Eiji Muramoto, Shinya Nunoue, Toshiyuki Oka
  • Patent number: 8987086
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: March 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Kuo-Chi Tu, Chun-Yao Chen
  • Patent number: 8987144
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Hans-Juergen Thees
  • Patent number: 8987856
    Abstract: A photodiode, a light sensor and a fabricating method thereof are disclosed. An n-type semiconductor layer and an intrinsic semiconductor layer of the photodiode respectively comprise n-type amorphous indium gallium zinc oxide (IGZO) and intrinsic IGZO. The oxygen content of the intrinsic amorphous IGZO is greater than the oxygen content of the n-type amorphous IGZO. A light sensor comprise the photodiode is also disclosed.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: March 24, 2015
    Assignee: E Ink Holdings Inc.
    Inventors: Fang-An Shu, Yao-Chou Tsai, Ted-Hong Shinn
  • Patent number: 8772946
    Abstract: A component can include a substrate and a conductive via extending within an opening in the substrate. The substrate can have first and second opposing surfaces. The opening can extend from the first surface towards the second surface and can have an inner wall extending away from the first surface. A dielectric material can be exposed at the inner wall. The conductive via can define a relief channel within the opening adjacent the first surface. The relief channel can have an edge within a first distance from the inner wall in a direction of a plane parallel to and within five microns below the first surface, the first distance being the lesser of one micron and five percent of a maximum width of the opening in the plane. The edge can extend along the inner wall to span at least five percent of a circumference of the inner wall.
    Type: Grant
    Filed: June 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Terrence Caskey, Kishor V. Desai, Huailiang Wei, Craig Mitchell, Belgacem Haba
  • Patent number: 8765604
    Abstract: The disclosure relates to a method of fabricating an interconnection structure of an integrated circuit, comprising the steps of: forming a first conductive element within a first dielectric layer; depositing a first etch stop layer above the first conductive element and the first dielectric layer; forming an opening in the first etch stop layer above the first conductive element, to form a first connection area; depositing a second dielectric layer above the etch stop layer and above the first conductive element in the connection area; etching the second dielectric layer to form at least one hole which is at least partially aligned with the connection area; and filling the hole with a conductive material to form a second conductive element in electrical contact with the first conductive element.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: July 1, 2014
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Patrick Vannier
  • Patent number: 7118985
    Abstract: A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: October 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Derryl D. J. Allman, Kenneth Fuchs
  • Patent number: 6908810
    Abstract: A method of preventing decreasing threshold voltage of a MOS transistor by formation of shallow trench isolation. Shallow trenches are formed to isolate first active regions and second active regions. The first active regions are located within a core circuit region, while the second active regions are located within a peripheral circuit region. A first ion implantation to form well regions is performed on the first and second active regions, respectively. A second ion implantation is performed on the second active region and edges of the first active regions to form second channel doping regions and to increase ion concentration at the edges of the first active regions, respectively. A third ion implantation is further performed on the first active regions to form first channel doping regions.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: June 21, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Chine-Gie Lou
  • Patent number: 6900084
    Abstract: A means of forming unevenness for preventing specular reflection of a pixel electrode, without increasing the number of process steps, is provided. In a method of manufacturing a reflecting type liquid crystal display device, the formation of unevenness (having a radius of curvature r in a convex portion) in the surface of a pixel electrode 108d is performed by the same photomask as that used for forming a channel etch type TFT, in which the convex portion is formed in order to provide unevenness to the surface of the pixel electrode and give light scattering characteristics.
    Type: Grant
    Filed: May 9, 2000
    Date of Patent: May 31, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6890827
    Abstract: To address the above-discussed deficiencies of the prior art, the present invention provides an integrated circuit formed on a semiconductor wafer, comprising a doped base substrate; an insulator layer formed over the doped base substrate; and a doped ultra thin active layer formed on the insulator layer, the ultra thin active layer including a gate oxide, a gate formed on the gate oxide, and source and drain regions formed in the ultra thin active layer and adjacent the gate. The present invention therefore provides a semiconductor wafer that provides a doped ultra thin active layer. The lower Ioff in the DRAM transistor allows for lower heat dissipation, and the overall power requirement is decreased. Thus, the present invention provides a lower Ioff with reasonably good ion characteristics.
    Type: Grant
    Filed: August 27, 1999
    Date of Patent: May 10, 2005
    Assignee: Agere Systems Inc.
    Inventors: Seungmoo Choi, Sailesh Merchant, Pradip K. Roy
  • Patent number: 6884636
    Abstract: A method of fabricating an infrared detector, a method of controlling the stress in a polycrystalline SiGE layer and an infrared detector device is disclosed. The method of fabricating includes the steps of forming a sacrificial layer on a substrate; patterning said sacrificial layer; establishing a layer consisting essentially of polycrystalline SiGe on said sacrificial layer; depositing an infrared absorber on said polycrystalline SiGe layer; and thereafter removing the sacrificial layer. The method of controlling the stress in a polycrystalline SiGe layer deposited on a substrate is based on varying the deposition pressure. The infrared detector device comprises an active area and an infrared absorber, wherein the active area comprises a polycrystalline SiGe layer, and is suspended above a substrate.
    Type: Grant
    Filed: May 18, 2001
    Date of Patent: April 26, 2005
    Assignee: Interuniversitair Micro-Elektronica Centrum (IMEC,vzw)
    Inventors: Paolo Fiorini, Sherif Sedky, Matty Caymax, Christiaan Baert
  • Patent number: 6818493
    Abstract: A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.
    Type: Grant
    Filed: July 26, 2001
    Date of Patent: November 16, 2004
    Assignee: Motorola, Inc.
    Inventors: Christopher C. Hobbs, Philip J. Tobin
  • Patent number: 6787447
    Abstract: Semiconductor processing methods of forming integrated circuitry are described. Embodiments provide a substrate having circuit devices. At least three layers are formed over the substrate and through which electrical connection is to be made with at least two of the circuit devices. The three layers comprise first and second layers having an etch stop layer interposed therebetween. Contact openings are formed through the three layers and a patterned masking layer is formed over the three layers to define a conductive line pattern. Material of an uppermost of the first and second layers is selectively removed, relative to the etch stop layer, to define troughs joined with the contact openings. Conductive material is subsequently formed within the joined troughs and contact openings. In some embodiment, contact openings are formed that have an aspect ratio of no less than about 10:1.
    Type: Grant
    Filed: September 11, 2001
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventor: John H. Givens
  • Patent number: 6767763
    Abstract: A method of mounting a component in which a component is thermally press-bonded onto a substrate with a conductive adhesive. The method includes a substrate heating step in which the substrate is heated to a temperature which is 20° C.˜40° C. below the glass transition point of a bonding resin contained in the conductive adhesive, and a thermal press-bonding step in which the component is thermally press-bonded onto the substrate heated to the aforementioned temperature with the conductive adhesive.
    Type: Grant
    Filed: October 27, 2000
    Date of Patent: July 27, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Kenji Uchiyama
  • Patent number: 6756302
    Abstract: The invention concerns a method of forming a layer of metal on a substrate and fill the via with high throughput. A layer of metal can be formed on a substrate using sequentially a cold deposition step, a slow hot deposition step and a rapid hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit a seed layer of metal over the entire surface on which the metal layer is to be formed. In the slow hot deposition step, further metal is deposited at a power allowing for surface diffusion of the deposited metal, which is then followed by a rapid hot deposition of metal under bulk diffusion conditions.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 29, 2004
    Assignee: Cypress Semiconductor Corporation
    Inventors: Ende Shan, Gorley Lau, Sam Geha