Abstract: The present invention describes the use of two semiconductor layers, a thin film (TF) layer and a bulk Si wafer layer, to make high density and high speed merged logic and memory IC chips. The memory cells use three-dimensional (3D) SRAM structures. Two kinds of 3D logic cells are disclosed. 3D form of the differential cascode voltage switch (DCVS) architecture, and a 3D form of the DCVS with pass gate (DCVSPG) logic architecture. A high density “system on chip” architecture is described. The high density is achieved by locating large PMOS transistors in the TF Si layer, and the fast NMOS transistors in a bulk Si wafer layer. A single process sequence to simultaneously make the logic and memory circuits on the IC chip is also described.

Abstract: A method for manufacturing capacitors is disclosed. The method is applicable to a capacitor whose upper electrode area is smaller than the lower electrode area. It is featured in that a material, such as a TiN hard mask, is inserted between the conventional electrode metal layer and photo resist layer. This enables one to perform the in-situ photo resist layer removal step after dry etching the upper electrode metal. Since the photo resist layer removal step uses oxygen plasma, the surface of the lower electrode polysilicon is formed with a protective oxide layer because the dielectric layer is etched during the process of dry etching the upper electrode metal. Using the disclosed method can solve the corrosion problem on the upper electrode metal and avoid the lower electrode polysilicon from being corroded by the wet etchant.

Abstract: In the semiconductor device manufactured by the manufacturing method of the present invention, the tungsten layer resistant to an impulsive force is formed without the oxide film layer existing below the second pad. Hence, if an external force is applied to the second pad through an opening upon bonding or the like, cracks are hard to occur. Accordingly, it is possible to provide a semiconductor device high in mechanical strength and reliability and a method of manufacturing.

Abstract: There are disclosed a semiconductor substrate having a non-porous monocrystalline layer with reduced crystal defects on a porous silicon layer and a method of forming the substrate. The forming method comprises a heat treatment step of heat-treating a porous silicon layer in an atmosphere not containing a silicon-based gas and the step of growing a non-porous monocrystalline layer on the porous silicon layer, wherein the heat treatment is conducted under the conditions such that the etched thickness of the silicon layer is 2 nm or less and that the rate of change r of the surface pore density of the porous silicon layer (r=surface pore density after heat treatment/surface pore density before heat treatment) satisfies the relationship 1/10000≦r≦1.

Abstract: This invention provides methods of forming a field-effect transistor in an integrated circuit using self-aligning technology on the basis of a sidewall spacer masking procedure, both for defining the device isolation features and the source and drain regions. The active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique. Thus, the present invention enables an increase of the integration density of semiconductor devices, a minimization of the parasitic capacitances in field-effect transistor devices, and a quicker manufacturing process.

Abstract: An insulating-gate semiconductor device has a first nitride semiconductor layer formed over a substrate and an insulating oxidation layer obtained by oxidizing a second nitride semiconductor layer formed on the first nitride semiconductor layer. A gate electrode is formed on the insulating oxidation layer.

Abstract: A method of fabricating a semiconductor device includes the steps of forming an insulation film on a compound semiconductor layer, forming an opening in the insulation film so as to expose a part of the compound semiconductor layer, forming a gate electrode of a refractory metal compound on the insulation film such that the gate electrode contacts with the compound semiconductor layer at the contact hole, and removing the insulation film by a wet etching process, wherein the wet etching process is conducted by an etchant to which both of the gate electrode and the compound semiconductor layer show a resistance.

Abstract: In a process of manufacturing semiconductor chips, first, the reverse of a wafer, on the obverse of which many chips are formed, is ground so as to shape the wafer with a predetermined thickness. Then, the reverse of the wafer is polished or etched so that the broken layer which is formed during the back grinding is removed. Next, grooves are formed on the reverse of the wafer in a predetermined depth along streets formed between the chips. Finally, the wafer is cleft along the grooves so as to be divided into separate chips. By this process, the broken layer formed on the reverse of the wafer is removed after the back grinding, then the wafer is divided into separate chips by use of the cleavage; therefore, chipping is effectively reduced.

Abstract: A thin film of precursor for forming a layered superlattice material is applied to an integrated circuit substrate, then a strong oxidizing agent is applied at low temperature in a range of from 100° C. to 300° C. to the precursor thin film, thereby forming a metal oxide thin film. The strong oxidizing agent may be liquid or gaseous. An example of a liquid strong oxidizing agent is hydrogen peroxide. An example of a gaseous strong oxidizing agent is ozone. The metal oxide thin film is crystallized by annealing at elevated temperature in a range of from 500° C. to 700° C., preferably not exceeding 650° C., for a time period in a range of from 30 minutes to two hours. Annealing is conducted in an oxygen-containing atmosphere, preferably including water vapor. Treatment by ultraviolet (UV) radiation may precede annealing. RTP in a range of from 500° C. to 700° C. may precede annealing.

Abstract: A slurry for CMP having a liquid and a plurality of polishing particles, wherein the polishing particle contains an organic particle and a plurality of inorganic particles, and the organic particle and the inorganic particles are unified by thermocompression bonding.

Abstract: The present invention provides an encapsulation method and apparatus that allows high throughput production of reliable, high quality board-on-chip packages, or other semiconductor die packages, from a multi-chip array arrangement on a carrier substrate. In an exemplary embodiment relating to a board-on-chip array, a mold is provided with an upper mold platen and a plurality of upper mold platen cavities for encapsulating wire bonds and related interconnections on a first side of a multi-chip carrier substrate. The mold further includes a lower mold platen and a lower mold platen cavity for encapsulating substantially the entire second side of the carrier substrate, to include a plurality IC chips mounted thereon in array fashion. Substrate support elements, in the form of standoffs pins or bosses, are provided for supporting the multi-chip carrier substrate during the encapsulation process.

Abstract: A gate electrode is made up of a lower electrode of polysilicon and an upper electrode including a low-resistance film. A nitride sidewall is formed to cover at least the side faces of an insulator cap and the upper electrode. A pad oxide film is formed to cover at least part of the side faces of the lower electrode and part of the upper surface of a semiconductor substrate. Since a second nitride sidewall is formed to cover the first nitride sidewall and the pad oxide film, a self-aligned contact hole can be formed by etching. As a result, a semiconductor device with a highly reliable self-aligned contact can be obtained.

Abstract: A method of forming on a common semiconductor body (substrate) silicon oxide layers of different thicknesses uses plasma treatment on selected portions of an original thermally grown silicon oxide layer. The plasma treated portions are completely etched away to expose a portion of the surface of the body while non-selected portions of the original silicon oxide layer are little effected by the etch. A thermally grown second layer of silicon oxide is formed with the result being that the silicon oxide layer formed in the exposed portions of the body is thinner than elsewhere. The use of dual thickness silicon oxide layers is useful with dynamic random access memories (DRAMs) as gate oxide layers of field transistors of memory cells of the DRAM typically require different electrical characteristics than transistors of support circuitry of the DRAM.

Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.

Abstract: A method is provided for forming a relaxed silicon germanium layer with a high germanium content on a silicon substrate. The method comprises: depositing a single-crystal silicon (Si) buffer layer overlying the silicon substrate; depositing a layer of single-crystal silicon germanium (Si1−xGex) overlying the Si buffer layer having a thickness of 1000 to 5000 Å; implanting the Si1−xGex layer with ionized molecular hydrogen (H2+) a projected range of approximately 100 to 300 Å into the underlying Si buffer layer; optionally, implanting the Si1−xGex layer with a species selected such as boron, He, or Si; annealing; and, in response to the annealing, converting the Si1−xGex layer to a relaxed Si1−xGex layer. Optionally, after annealing, an additional layer of single-crystal Si1−xGex having a thickness of greater than 1000 Å can be deposited overlying the relaxed layer of Si1−xGex.

Abstract: A memory device includes a first memory cell and a second memory cell both controlled by a common control gate. The device includes: a substrate; first and second stacks each including an insulating layer formed over the substrate, a first conductive layer formed over the insulating layer and providing a select gate, and a first dielectric layer formed over the first conductive layer, each of the stacks also including an inner sidewall and an outer sidewall, the. stacks being separated by a common area of the substrate, the inner and outer sidewalls of the stacks being coated with a second dielectric layer; first and second spacers formed adjacent the inner sidewalls of the first and second stacks respectively, the first and second spacers being separated by a medial portion of the common source area of the substrate, each of the spacers.

Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.

Abstract: On a transparent substrate to which a gate electrode is arranged, a silicon nitride film and a silicon oxide film to be gate insulating films are deposited, and further, a polycrystalline silicon film as a semiconductor film to be an active region is formed. On the polycrystalline silicon film corresponding to the gate electrode, a stopper is arranged, and a silicon oxide film and a silicon nitride film to be an interlayer insulating films are deposited so as to cover this stopper. The film thickness T0 of the stopper is set in a range of 800 angstroms to 1200 angstroms. Furthermore, the film thickness T0 of the stopper is set in the range to fulfill the following expression: T0+T1≦(T2×8000 Å)½ where T1 is the film thickness of the silicon oxide film and T2 is the film thickness of the silicon nitride film.

Abstract: A semiconductor structure (and method for manufacturing the same) comprises an active array of first elements having a first manufacturing precision, a peripheral region surrounding the active array, the peripheral region including second elements having a second manufacturing precision less than the first manufacturing precision, wherein the second elements are isolated from the active array and comprise passive devices for improving operations of the active array.

Abstract: A method for etching an insulating layer without damage to the conducting layer and associated liner layer within the insulating layer. A dielectric layer is deposited on a semiconductor substrate and then patterned. A liner layer and a conducting layer are then deposited within the patterned dielectric. A passivating layer is deposited on top of the conducting layer after the conducting layer has been planarized through chemical-mechanical polishing while simultaneously etching the dielectric layer through a process that does not damage the underlying conducting and liner layers. The insulating layer is preferably a dielectric such as silicon dioxide and the liner layer is tantalum, tantalum nitride or a combination of the two. The passivating layer preferably consists of carbon and fluorine bound up in various chemical forms. The conducting layer preferably consists of copper.