Abstract: An apparatus and method for restreaming data that has been queued in a bus bridging device. Data received via a first bus is stored in a first queue. A first portion of the data is output from the first queue onto a second bus while a second portion of the data remains in the first queue. In response to another data value being transferred from the first bus to the second bus before the second portion of the data is output to the second bus, the second portion of the data in the first queue is invalidated.

Abstract: An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1) log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: A high sample rate cosine filter eliminates DC components by summing them such that they sum to zero. A non-orthogonal cosine filter is also provided. When the cosine filter is applied for N=4 samples per cycle, the samples are separated by 90 degrees. However, at higher sampling rates, it is not necessary to wait for 90 degrees to estimate the phasor value. Non-orthogonal components are used to estimate the phasor value. The time delay associated with the cosine filter is reduced in the process.

Abstract: A bus bridge which can prevent invalid data from being transferred from a secondary PCI bus to a primary PCI bus even when an SCSI controller or another device provided with a memory the content of which is cleared after a read, is connected to the secondary PCI bus. In a controller, a transaction is processed as a delayed transaction. A combination circuit generates a switching logic signal in accordance with a command or an address included in the transaction. In accordance with the memory content, a bus release controller restricts transmission by a transaction forward controller of a control signal for stopping the transaction issued on the primary PCI bus. Instead of restricting the transmission of the control signal, the time-out period of the buffer memory may be prolonged.

Abstract: A bus card for connecting to a local bus of a computer system comprises a connector for connecting to the local bus, a peripheral interface controller for enabling communication between a peripheral device and the local bus, video processing circuitry having connectors to enable input and output of video signals, and a bridge circuit that enables the peripheral interface controller and the video processing circuitry to share the connection to the local bus of the computer system.

Abstract: A device for terminating a bus configured to have one or more processors coupled thereto. The device comprises a support member having a termination circuit which is coupled to a conductor of the bus when the support member is coupled to the bus. In one embodiment, the support member is coupled between the bus and the processor. In another embodiment, the support member is connected to the bus separately from the processor. The support member may include an auxiliary circuit in addition to the termination circuit which may be used to correct, supply, or update signals transmitted on the bus.

Abstract: A locking system has a double locking mechanisms such that when a main body of an electronic equipment and an extension device are combined, an operability similar to that in case of using a single equipment is maintained and the combination is not separated at the time of carrying and which enables a more intelligent control by a built-in MPU and in which a high reliability is obtained. In an electronic equipment system in which a main body and an extension device are freely combined, an open-close-lever which is interlocked with movable claws is arranged on the side surface of the extension device, retaining holes to fix the movable claws are formed in the main body, an electronic locking unit comprising a mechanism having a cam portion adapted to lock the opening or closing of the lever and an electronic motor for making the cam operative is installed in the extension device. The movable claws couple and fix the main body and the extension device by closing the open-close-lever.

Abstract: The present invention provides method and system aspects for performing error data gathering from fault isolation registers of a computer system following a machine check occurrence. A method aspect includes utilizing firmware to perform failure information retrieval in software accessible registers and initiating a service processor (SP) for failure data retrieval in non-software accessible registers. The method further includes coordinating the combination of the failure information retrieved and the failure data retrieved in an error log for use in isolation of a fault source in the computer system.

Abstract: A network adaptor that generates interrupts to a host system when data is received from the network or downloaded from system memory for transmittal over the network. The adaptor generates interrupts after a delay determined by an interrupt deferral mechanism, which includes one or more timers and/or one or more counters. Interrupts are generated, for example, after a predetermined time has elapsed after a DMA completion or after a certain number of packets are counted.

Abstract: A power distribution unit that can detect system status includes: an optional line filter, a live power source for driving a I2C device, a power sensor which monitors system power status in connection with the I2C device through a I2C BUS, and a relay and on/off switch circuit which turns on/off system power in accordance with the I2C device through the I2C BUS.

Abstract: A system and method for high speed transferring of bus operations which are preferably strictly ordered in a processing system is provided. A system and method in accordance with the present invention comprises issuing a plurality of bus operation requests by a processor and determining if a first response has been received by the same processor indicating that one of the plurality of bus operation requests should be reissued. Then, if the first response is received, the processor provides a second response indicating that at least another of the issued bus operation requests should be reissued.

Abstract: A system and method for controlling the flow of information between devices. A count is maintained representative of requests issued by a first device. The count is incremented for each packet issued by a first device and decremented for each packet received at the first device. A maximum buffer count, which corresponds to the capacity of the buffer is used to perform flow control by determining when the maximum buffer count is to be exceeded by the issuance of a packet by the first device. If the count is to be exceed, issuance of packets by the first device is prevented until the maximum buffer count will not be exceeded by issuance of the packet.

Abstract: A technique allowing a terminal device located in a remote place to protect data existing on an information processing system and then control an electric source of the information processing system is provided. An information processing system according to the present invention includes a service processor for discriminating an order issued by a terminal device located in a remote place, an electric source control circuit for controlling connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the service processor, and an electric source unit for conducting connection or disconnection of an electric source in response to an electric source connection or disconnection order issued by the electric source control circuit.

Abstract: A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications.

Abstract: A device and method for interconnecting two universal serial buses (USBs) is provided in which the device controls the current supplied to the device from the USBs via a power manager. In particular, when one or both of the buses connected to the device enter a suspended state, the power manager reduces the current consumed by the device so that the device does not exceed a maximum suspend current. The device may also have a power manager controller which permits one or both device drivers connected to the USBs to control the power manager.

Abstract: An apparatus and method minimizes processing resource of a host system during service of interrupts generated closely in time by at least one peripheral device. The present invention determines, before the end of a prior interrupt service routine for a prior interrupt, a predicted interrupt time point when a subsequent interrupt will be generated by the at least one peripheral device. The host system operates in a polling mode if the predicted interrupt time point is before a predetermined time period after the end of the prior interrupt service routine. Thus, the host system avoids the processing resources needed for context switching time when the subsequent interrupt is generated closely in time from the prior interrupt. The host system operates in an interrupt mode if the predicted interrupt time point is after the predetermined time period after the end of the prior interrupt service routine.

Abstract: A printed circuit card having first and second circuit units mounted thereon in connection to terminal pads adjacent two card edges, with the first and second circuit units being in connection to each other and to select pads of a first edge such that upon insertion of that edge into a given card socket, both circuit units are enabled, and the circuit units also being in connection to the pads of a second edge such that upon insertion of that edge into a second card socket, only the second circuit unit is enabled. In the preferred embodiment, the card is a memory module card having buffer and memory circuit units designed to cooperate with each other and with either of standard, buffered or unbuffered memory card sockets in a system board in accordance with insertion of a first or second pad edge in one of the card sockets to automatically provide, either combined circuit unit operation, or single circuit operation. The invention is also applicable to clocked register circuits and series pass devices.

Abstract: An apparatus is provided to handle classes of data in computer systems that must not be permitted to intermingle due to their security classifications or criticality of their data content, as in banking or safety applications. An isolated path is established for transmitting a given class of data between elements of the computer system with assurance that the data has been transmitted from the proper source, has been received by an authorized recipient and that unauthorized elements of the system have not intercepted or altered the data. Plug in type secure bus arbiter (SBA) module or bus arbiter interconnect module (10) with a controller (11) provide a way to isolate data without modification of the computer back plane or motherboard in a computer chassis (12). Modules can be used with commercial off the shelf (COTS) and non-development item (NDI) cards for a wide variety of standard computer printed circuit boards.