Abstract: A tri-state signal driver circuit includes a signal driver circuit to generate a driven signal. A tri-state enable logic circuit generates a pass gate disable signal corresponding to a tri-state command signal. A demultiplexer connected to the signal driver circuit and the tri-state enable logic circuit includes a set of pass gate switches to route the driven signal to a selected output node of the demultiplexer. The set of pass gate switches are responsive to the pass gate disable signal so as to produce a tri-state output signal at the selected output node.

Abstract: A data processing device uses a processor such as a central processing unit and a special-purpose hardware circuit, such as an accelerator for accelerating the software operation using the operation program of the processor by replacing the software operation partially by the hardware. A practical application of this processor arrangement is found in mobile communication terminal devices including a digital cellular portable telephone in which a digital signal processor of a mobile communication terminal device operates in association with an accelerator for accelerating specific signal processings such as waveform equalization. The processor provides input data to the accelerator and the results of operation by the accelerator are output to a register or memory based on a cycle of operation to be read periodically by the processor.

Abstract: A method and apparatus to prevent invalid data from propagating into devices connected to a PCI tristate bus is provided. The method and apparatus utilize the PCI bus control signals to monitor the bus transaction's mode (e.g., as a bus target or as a bus master), type (e.g., read, write), and status (e.g., ongoing bus transaction). Using these information, control the opening and closing of a window gate hardware to allow valid data to propagate into a device connected to the PCI tristate bus and to prevent invalid data from propagating into the device.

Abstract: A system and method for transforming specialized data files of a first computer system into industry-standard byte-stream files usable for a second system or other systems. First and second programmatic interfaces of the first system can take the specialized format native data files and transform them into standard formatted byte-stream data files for placement in a storage media of a second computer system which can then be initiated to use a CD Writer package to cause the data files to burned on to a CD-ROM. This CD-ROM can then provide the byte-stream data file for use in many different types of platforms.

Abstract: A computer system is formed using a right angle processor connector assembly and a right angle add-on card connector. The right angle processor connector assembly includes a right angle processor connector and a complementary support member. Each of the right angle processor package and add-on card connectors includes an L-shaped body having an inner cavity defined a number of inner walls extending from one end to the other end. Each connector is mechanically attached to a motherboard, upside down and in a direction orthogonal to the motherboard. Each connector receives its constituent component (i.e. the processor package or the add-on card) through one end, with the constituent components and the motherboard occupying parallel planes. Each connector further includes a number of L-shaped pins disposed on the inner walls extending from one end through the other to electrically couple the constituent component to the motherboard.

Abstract: A bridge circuit passes digital information between a primary PCI bus and a secondary PCI bus with increased throughput. The PCI busses carry digital information using respective clock signals having a known minimum skew therebetween. The interface bridge circuit includes primary and secondary PCI bus interfaces configured and arranged to communicate with the primary and secondary PCI busses respectively, and a memory buffer configured and arranged to store the digital information and to be accessed by the primary and secondary PCI bus interfaces. Further, a programmable configuration register is configurable in response to digital configure information received from the primary bus, and is adapted to provide an enable signal to one of the primary PCI bus interface and the secondary PCI bus interface. The enable signal indicates that the digital information is ready in the memory buffer for access by the one of the primary PCI bus interface and the secondary PCI bus interface.

Abstract: A power control circuit and corresponding technique for controlling the reduction or augmentation of operating frequency and/or supply voltage utilized by an electronic device. Such control is based on the operating environment of the hardware product employing the electronic device by determining whether the hardware product is interconnected to an external source having at least one enhanced cooling mechanism. As a result, the hardware product is able to operate at full frequency and voltage during certain situations and to operate at a reduced frequency and/or voltage during other situations.

Abstract: A bus connects a first and second integrated circuit. The bus includes a frame sync line which indicates the beginning of a frame when asserted, each frame containing a predetermined number time slots. A data out line provides data from the first to the second integrated circuit. The data represents the state of signals to be provided on output terminals of the second integrated circuit. Each of the data bits is assigned one of the time slots in the frame. A data in line provides a predetermined number of second data bits from the second to the first integrated circuit during each frame. Each of the second data bits is assigned one of the time slots and includes data including data bits indicating the state of input terminals of the second integrated circuit. A clock signal defines the time slots within the frame. The bus operates to provide frames substantially continuously between the first and second integrated circuit while the first and second integrated circuits.

Abstract: A method and apparatus for setting a priority sequence among a plurality of requesters using a common destination within a computer system. An advantage is that all requesters contending for the common destination will have timely access with respect to all other competing requesters. In a first exemplary embodiment of the present invention, a priority controller can use a two-level priority scheme to select the next requester. The first level of priority alternates between an external requester and an on-card requester where every other set of data is from the external requester. The second level of priority alternates between on-card modules during an on-card priority cycle. In an alternative exemplary embodiment, the priority controller can stack a request to transfer acknowledge and data information from an external requester if it is busy. The priority controller also prevents sending an acknowledgment/data cycle out to an external source to prevent sending more data than the FIFO stacks can accommodate.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A multiprocessor computing system has memory shared by all processors of the computing system and includes an symmetric multiprocessor (SMP) operating system and at least one external device controlled by a device driver. The device driver is typically written to run in a uniprocessor environment. A method for protecting the execution state of the device driver uses a pair of "collaborative" spinlocks, an interrupt time spinlock and a task time spinlock. At task time, prior to calling the device driver, the task time spin lock is acquired by the operating system. The operating system then waits until the interrupt time spinlock is in an "unowned" state before calling the device driver. Upon return from the device driver, the operating system releases the task time spinlock. At interrupt time, prior to calling the device driver's interrupt handler, the interrupt time spinlock is acquired by the operating system. The operating system then determines if the task time spinlock is owned.

Abstract: In the case of a card cage for an electronic control unit having signal-processing analog and/or digital components, high-speed digital components, as well as components having both signal-processing functional parts, as well as high-speed digital functional parts and power components, which are arranged on a multilayer printed-circuit board and are electroconductively connected to a shared ground plane, the signal-processing components of each module having a shared connection to the common ground plane, the radiated interference from the control unit produced by high-frequency interference currents can be reduced, and high current densities in the ground plane and resultant potential shifts can be prevented from adversely affecting the signal processing, in that the signal-processing components are combined into signal-processing modules having at least one shared function, and the ground connections of all components of such a functional module are routed in each case via conductor connections to a common

Abstract: Interface processor (IP)(50) sends and receives data units to and from an external host and a processor. The IP is capable of simultaneous, full duplex operation via high speed serial and parallel interfaces. The IP provides a highly flexible and configurable interface which is capable of interfacing to a variety of systems with minimal external hardware. The IP also provides a method of converting received data into data packets. The IP provides buffering of multiple data packets for use in systems having "bursty" data traffic. The IP has a memory expansion capability allowing for changeable buffer capacities.

Abstract: A free-space intra-shelf interconnect system is provided in which each of a number of circuit boards in a shelf communicates with any other board through free-space interconnects. Each board is equipped with a free-space transmit coupler to transmit a signal to a free-space receive coupler of an adjacent board. Simply sliding the boards in the shelf and latching them in place as usual, automatically aligns the transmit and receive couplers for optimum coupling. System configurations are provided for building a closed communication loop within the shelf, that allows for data communications between any board within the shelf. Logical addressing allows for interchangeability of boards within a shelf. This, in turn, allows for moving a defective board to the end positions of a shelf for debugging purposes. An extender board for testing and debugging purposes is also provided if free physical access to both board surface areas is simultaneously needed.

Abstract: A PCI bus to IEEE 1394 bus translator for coupling a PCI device to a host computer via an IEEE 1394 bus. The translator translates addresses of PCI bus cycles initiated by the PCI device into 1394 memory addresses and performs data transfers between the PCI device and host computer by exchanging 1394 request and response packets with the host computer using the translated 1394 memory address. The translator also translates 1394 memory addresses of 1394 request packets received from the host computer into PCI cycle addresses and performs data transfers between the PCI device and host computer by initiating PCI bus cycles targeted at the PCI device using the translated PCI bus cycle addresses. The translator posts data from sequential PCI bus write cycles initiated by the PCI device into a write-posting FIFO until granted ownership of the 1394 bus. The translator combines the PCI write cycle data into a single IEEE 1394 write request packet and transmits the packet on the 1394 bus to the host computer.

Abstract: In a multi-processor system, the semaphore device comprises a latch associated by software or hardware to a non-shareable resource. The output of the latch is connected to the bus for the re-reading of the semaphore by the processors. The output of the latch is also connected to an input of a multiplexer connected by its other input to the write bus of the semaphore. The control field output of the latch is connected to an AND gate receiving, at its other input, the control bit of the bus and conditioning, by its output, the writing of the latch. The task seeking to appropriate the semaphore tries to write its unique identifier in the latch with the control field at <<1>>. It then re-reads the semaphore register. Equality between the value re-read and the value written means that the task has succeeded in appropriating the resource. The source is released by the writing of the control field at <<0>>.

Abstract: A simplified serial data bus provides interconnection between equipment such as computers, imaging apparatus, and consumer electronic devices. The simplified bus utilizes the cable and connectors of a data bus standard. An apparatus for data communication comprises a connector for receiving a plurality of signal carrying conductors. A control circuit is coupled to the connector for supplying a control signal to one of the plurality of conductors. A detector is coupled to the connector for detecting a voltage source on the one of the plurality of conductors. The control signal is inhibited responsive to detection of the voltage source.

Abstract: This invention provides a method of estimating the power consumption of a microprocessor with the use of an instruction file that is simple and easy to prepare. A microprocessor (3, 4) reads instructions out of a main memory (2) or an instruction cache (1) and executes them. A group of instructions that include at least one target instruction whose power consumption is to be estimated is repeatedly executed in simulations, to find the power consumption of the microprocessor on the target instruction in a cache miss state, as well as the power consumption of the microprocessor on the target instruction in a cache hit state, according to the power consumption of the microprocessor in given cycles.

Abstract: At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID number, not associated with a CPU in the same cluster, is associated with the opposite CPU cluster that appears to the original cluster as a "phantom" processor. A round-robin bus arbitration scheme allows ordered ownership of a common bus within a first cluster until the ID reaches the "phantom" processor, at which time bus ownership passes to a CPU in the second cluster. This arrangement is preferably symmetric, so that when a CPU from the first cluster requests ownership of the bus, it is granted bus ownership by virtue of the first cluster's appearance to the second cluster as a "phantom" CPU.

Abstract: A data processing device 100 uses a portion of a random access memory 111 as an input buffer for holding a portion of a stream of data which is received by an input interface 130. Likewise, a portion of a memory 121 is used as an output buffer for holding a portion of processed data which is output by an output interface 140. A processing unit 110 within the processing device manages the flow of input and output data. The input interface asserts an I/O request 860 when it receives a data word, and the output interface asserts an I/O request 870 when it needs a data word. In response to an I/O request, fast interrupt circuitry inserts a ghost instruction which is formed by doppelganger circuitry into an instruction sequence which is being accessed from a ROM 112. The ghost instruction performs the requested data transfer.