Abstract: A method and apparatus to prevent data from being corrupted prior to reaching the final destination is provided. The method and apparatus monitors the status of posted write transactions and transaction initiations. If it is determined that a posted write transaction is incomplete and there is a pending transaction initiation, a bus retry is requested for the pending transaction.

Abstract: One aspect of the invention relates to a method for arbitrating simultaneous bus requests in a multiprocessor system having a plurality of devices which are coupled to a shared bus. In one version of the invention, the method includes the steps of receiving a plurality of bus requests from the devices; determining a device having the highest priority; determining whether the device having the highest priority is requesting the bus; granting bus access to the device having the highest priority if the device having the highest priority is requesting the bus; sequentially searching, beginning from the device logically adjacent to the device having the highest priority, for a next requesting device, and granting bus access to the next requesting device if the device having the highest priority is not requesting the bus; and assigning the highest priority to the device logically adjacent to the next requesting device.

Abstract: A method and apparatus are provided for controlling communications on a small computer system interface (SCSI). A cache memory is arranged for storing an input queue, a status queue and a cache operation queue. An input engine detects unsolicited data from the SCSI and transfers the detected unsolicited data to the input queue. A status engine transfers status information between the SCSI and the status queue. A cache engine transfers data between the SCSI and the cache operation queue. Each of the input engine, the status engine, and the cache engine is independent to enable full duplex operation. A connection arbitrator is shared between the input engine, the status engine, and the cache engine enabling a connection to be shared by the input engine, the status engine, and the cache engine.

Abstract: A bus connects a first and second integrated circuit. The bus includes a frame sync line which indicates the beginning of a frame when asserted, each frame containing a predetermined number time slots. A data out line provides data from the first to the second integrated circuit. The data represents the state of signals to be provided on output terminals of the second integrated circuit. Each of the data bits is assigned one of the time slots in the frame. A data in line provides a predetermined number of second data bits from the second to the first integrated circuit during each frame. Each of the second data bits is assigned one of the time slots and includes data including data bits indicating the state of input terminals of the second integrated circuit. A clock signal defines the time slots within the frame. The bus operates to provide frames substantially continuously between the first and second integrated circuit while the first and second integrated circuits.

Abstract: A communication system and method of communicating including a slave function connected to a master function by a single address bus, a write data bus and a read data bus so as to allow for overlapping multiple cycle read and write operations between the master function and the slave function. Preferably the communication system includes a plurality of slave functions connected to a master function by the single address bus, the write data bus and the read data bus. A plurality of master functions may be connected to the slave functions through a bus arbiter connected to the plurality of master functions by an address bus, a write data bus and a read data bus for each master function. The bus arbiter receives requests for communication operations from the plurality of master functions and selectively transmits the communication operations to the slave functions.

Abstract: A mechanism to effectively retrieve residual data received from a serial data source is provided. As the shift register receives serial data from the serial data source, the activities and content of the shift register is monitored. Status bits are set to reflect the activities and content. These status bits are used to determine whether the shift register contains residual data and whether such residual data should be ignored the serial data received from the serial data source is output to a destination.

Abstract: A bus controller connects to external devices having both a separate-type bus interface and a multiplexed-type bus interface simultaneously by providing a dedicated address terminal and a time-division-multiplexed address/data terminal in the same bus controller. A selector connects a first address bus (A0 through A7) to the combined address/data terminal. Additionally, the first address bus is connected to the dedicated address bus terminal. Hence, the bus controller can interface with external devices designed for either type of terminal without requiring an adapter.

Abstract: A multiple bus master computer system employs an interface to a central processor allowing external bus masters to query the central processor with addresses and to receive back translated addresses. A first preferred embodiment employs two signals namely: translation request and translation address strobe to request/acknowledge the request for translation. The translation request is maintained asserted by one of the alternative bus masters until the central processor acknowledges it--at which time the alternative bus master drives an address (for example a virtual address) onto the address bus for translation. The central processor then translates the virtual address to its corresponding physical address (doing any page table walking or page faulting) and drives this physical address out on the address lines and asserts another translation address strobe.

Abstract: A multiple supply voltage peripheral component interconnect (PCI) connector is disclosed which replaces connectors that are keyed for a specific signaling voltage. A single connector receives all current types of PCI keyed card edge connectors and supplies the correct signaling voltage thereto. The type of PCI card is identified and the appropriate signaling voltage is switched to the signaling power input (Vio) using industry standard conditions at selected pin locations rather than using unique keying of cards and connectors to assure a match between the signaling voltage required by the card and the signaling voltage supplied at the connector. As shown, detection and control circuitry senses the presence of grounded or open conditions at selected pin locations indicative of the type card present in the connector and switches the signaling power supply to the correct voltage source.

Abstract: A controller for a smart battery selector included in a portable device has a plurality of switch-drivers at least equal to a plurality of smart batteries. The batteries provide battery-state data via a bus to a host computer included in the portable device. Each switch-driver effects selection of an associated battery. A control electronic-circuit in the controller directs operation of the switch-drivers for selecting the battery so that at any instant only one battery powers the portable device. A bus-snooper circuit permits the controller to independently monitor the bus for battery-condition alarm-messages. The controller may respond to such messages by selecting a different battery. The controller may also select a single battery for recharging, and may terminate charging upon receiving a battery overcharge message.

Abstract: A PCI interface includes a PCI core that operates at the PCI bus frequency and glue logic which provides an interface to a higher frequency clock domain. The glue logic includes FIFO buffers for addresses and data coming from or going to the PCI bus, and synchronizers for control signals coming from or going to the PCI core. In one embodiment, a novel synchronizer includes three flip-flops at least two of which are JK flip-flops.

Abstract: A method is provided of requesting use of a shared resource in a computer system. The method is suited to applications in which the device requesting use of the resource can predict the need for the resource before the need actually arises. A request for use of the resource is characterized by a latency between the request and a subsequent granting of the request. The latency has both a deterministic component and a non-deterministic component. In response to an initialization of the computer system, the deterministic component of the latency is measured. The use of the resource is then requested by the requesting device some predetermined time before the time at which the need for such use arises. The predetermined time corresponds to the deterministic component of the latency. The amount of local buffering required within the device is therefore chosen to accommodate only the random latency component.