Abstract: A scheme for arbitrating access to a data bus shared among a plurality of competing sources is provided. Each competing source is assigned an adjustable priority weighting value (PWV) which is initially set to an initial value based on the bandwidth requirements of the competing source. During arbitration, the PWVs of those competing sources requesting access to the bus are compared, and the competing source with the smallest PWV is granted access. The PWV of the competing source which was granted access to the bus is reset to its initial value and the PWV of each competing source which requested, but was denied, access is reduced by one for subsequent comparisons. The arbitration scheme of the present invention is further applied to two-level arbitration. Each competing source is classified into a competing source group, and the requests from the grouped competing sources are processed by first level arbitration. First level arbitration passes one competing source for each group to a second level arbiter.

Abstract: An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent, a retry identification register, and a completion counter. The initiator PCI agent is adapted to couple to a PCI bus and communicate with a target PCI agent via the PCI bus by initiating a data transaction. The retry identification register is coupled to the initiator PCI agent. The retry identification register is adapted to store a target address and a transaction type corresponding to the target PCI agent when the target PCI agent issues a retry to the initiator PCI agent. The completion counter is coupled to the initiator PCI agent and is adapted to measure a latency period of the target PCI agent.

Abstract: An apparatus for and a method of arbitrating a stream of access requests over multiple outputs. In one embodiment, the apparatus is implemented with D*[W+(N+1)log.sub.2 D] storage elements, where D is a maximum number of outstanding requests allowed by an issuing agent, N is a number of different request types, and W is a width of access requests measured in bits. The present embodiment comprises a main queue, an input address selection circuit coupled to the main queue for selecting storage locations to receive a stream of access requests, and a plurality of output address selection circuits coupled to the main queue for selecting storage locations to be read. Significantly, the input address selection circuit includes an input address list pointing to vacant storage locations in the main queue, and the input address list is updated each time an access request is stored in, or read out from, the main queue.

Abstract: The object of the present invention is to eliminate, in a data processing system having multiple buses, a combination of devices that can not be accessed via a PCI to PCI bridge. When an access request is issued to an S.sub.-- ISA device by an S.sub.-- PCI device, a PCI to PCI bridge determines whether or not a requested address is outside a blocked area, and whether or not the address matches an address stored in a retry register. When the requested address does not match the address in the retry register, the PCI to PCI bridge mistakes the access request for an access to a P.sub.-- PCI device. Thus, the PCI to PCI bridge positively decodes the access request on the S.sub.-- PCI bus, and transmits an access request on the P.sub.-- PCI bus. However, since none of the P.sub.-- PCI devices do not decode the request, the PCI to PCI bridge has to terminate the bus cycle on the P.sub.-- PCI bus by master abort.

Abstract: An arbiter uses a history based bus arbitration scheme to more fairly allocate a shared resource among multiple devices. The arbiter uses a history queue to dynamically update the priorities of the devices using the shared resource, and makes the grant decision in a single calculation using the combination of the history queue and requests from bidding devices. The priority for granting master to each device is dynamically modified so that the least recently serviced requestor will be granted the shared resource. A hidden arbitration scheme provides more fair history based resource allocation. A bus retry scheme demotes priority for processing devices that are assigned bus master but do not perform bus operations within a predetermined number of clock cycles. The arbiter also prevents bus grants during hot swap operations.

Abstract: A system ling client computers, particularly client notebook computers, to communicate with a computer local area network (LAN) using infrared or other transparent links. The system includes a pseudo nic driver, transparent communication hardware, and a transparent link in a network interface unit. The pseudo nic driver hides the technical details of the transparent communications by presenting itself as a traditional nic driver to the client networking software. The network interface unit bi-directionally communicates via the transparent link with an, for example, an infrared enabled client computer and performs the necessary bridging between the low level infrared signals and traditional LAN system such as Ethernet.

Abstract: An interrupt controller comprises a plurality of interrupt handling elements that are given different identification numbers for identification to which priorities are assigned. A first priority encoder accepts a plurality of level signals which are given different level numbers respectively representing the priorities assigned to the identification numbers, and then encodes the level number assigned to the highest-priority level signal included among all level signals at a low potential so as to generate an interrupt level number representing the encoded level number.

Abstract: A method, apparatus, and article of manufacture for generating signals using a Universal Serial Bus (USB) host controller and USB keyboard. Data generated by the keyboard is marked as being used with an operating system which responds to keyboard generated interrupts and which reads keyboard data stored in a register. The marked data is detected after it is received from the keyboard and is transferred to a register. An interrupt to a central processing unit (CPU) is then generated in response to the marked data being transferred to the register.

Abstract: A multiprocessor system includes a plurality of processors. A debugger interface includes interface circuitry to interface the plurality of processors to a debugger. The debugger interface includes means for receiving a debugger command from the debugger. Debugger command directing means determines from the debugger command for which of at least one of the plurality of processors the debugger command is intended, directs the debugger command, via the interface circuitry to the at least one intended processor. A processor command is received from one of the plurality of processors, and processor command directing means directs the processor command, received from the one processor, via the interface circuitry to the debugger. The system is especially suited for debugging software that is executing on the plurality of processors of the multiprocessor system.

Abstract: A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU's internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock.

Abstract: A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: A plurality of output terminals from which the power from an uninterruptible power supply apparatus is supplied. A timing holding unit holds timing information of power supply start and/or stop of respective ones of the plurality of output terminals, the timing information being set independently for each one of the plurality of output terminals. A timing pulse generating unit generates timing pulses which are used for reading out the timing information from the timing holding unit. Power supply start and/or stop of each output terminal is performed based on the timing information read out from the timing holding unit.

Abstract: A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.

Abstract: A bus bridge situated between two buses includes two queues: an outbound request queue and an inbound request queue. Requests originating on the first bus which target a destination on the second bus are placed into the outbound request queue. Requests originating on the second bus which target a destination on the first bus are placed into the inbound request queue. A transaction arbitration unit (TAU) within the bridge maintains transaction ordering and avoids deadlocks. The TAU determines whether requests can be placed in the inbound request queue. The TAU also determines whether requests originating on the first bus can be responded to immediately or whether the agent originating the request must wait for a reply. In addition, the TAU includes logic for determining whether a request in the outbound request queue can be executed on the second bus.

Abstract: A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.

Abstract: An apparatus for a distributed system having a plurality of nodes and a switch network for passing messages between nodes, each message being sent from a source node to a target node. Each node is connected to the switch network by an adapter having a count register for adding the value of the packets in messages received by the adapter to the value in the count register and a threshold register for containing a desired threshold value. An interrupt generator generates interrupts when the value in the count register is equal to or greater than the value in the threshold register. The value in the threshold register may be changed under program control to enable or disable interrupts.

Abstract: A microprocessor includes a register file that contains registers for storing pieces of data for use by execution units that receive the pieces of data through source ports. A bypass cache includes data registers into which pieces of data from the execution units are written. Data can be written to and read from the bypass cache in fewer clocks cycles than it can be written to and read from the register file. A content addressable memory array (CAM) includes address registers into which destination addresses are written which correspond to the pieces of data in the data registers. In the case of a particular piece of data, the particular data register into which the piece of data is written and the particular address register into which the corresponding destination address is written is controlled by the position of a write pointer provided by a rotating write pointer unit. The CAM includes a comparators that compare the destination address with a source address.