Patents Examined by Fritz Fleming
  • Patent number: 10094546
    Abstract: The technology described in this document is embodied in a sensor platform that includes an enclosure for housing one or more sensors, the enclosure configured to be deployed between a streetlight and a streetlight controller that manages operations of the streetlight. The sensor platform also includes an electrical receptacle for receiving the streetlight controller in a substantially secure configuration. The sensor platform also includes an electrical connector for connecting the enclosure to the streetlight. The sensor platform also includes at least one pass-through connector disposed within the enclosure to provide an electrical connection between the electrical connector and the electrical receptacle.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: October 9, 2018
    Assignee: CIMCON Lighting, Inc.
    Inventors: Anil Agrawal, Terrance Riedel
  • Patent number: 7768767
    Abstract: The ignition system is for use in a gas turbine engine. It comprises an ignition plug having a triggered spark gap therein.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: August 3, 2010
    Assignee: Pratt & Whitney Canada Corp.
    Inventor: Kevin Allan Dooley
  • Patent number: 7631114
    Abstract: The serial communication device capable of reducing the load on the CPU is provided for a system using the serial communications such as the car navigation system. The attention is focused on the control method of the serial communication, in which a DMA controller is used for the data reception in the serial communication, and a number larger than the number of data received at a time is set in advance as the number of transfers of the receive DMA controller, and further, the function to generate the timeout interrupt when data is not received for a certain period is added to the serial interface, so that the serial communication can be controlled and performed without applying the load on the CPU.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: December 8, 2009
    Assignees: Renesas Technology Corp., Alpine Electronics, Inc.
    Inventors: Kenji Kamada, Yoichi Onodera, Yasumasa Suzuki
  • Patent number: 7480786
    Abstract: Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction sets and conform to different bus interface protocols. A bus interface unit is coupled to an existing processor in a PLD. The bus interface unit is implemented using the programmable logic resources of the PLD, while the existing processor can be a dedicated processor or an existing “soft” processor. The bus interface unit acts as a peripheral device to translate bus transactions from the existing bus protocol (i.e., the bus protocol understood by the existing processor) to the target bus protocol. In addition, a stored emulation program emulates the target instruction set while executing instructions using the instruction set supported by the existing processor.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventor: Eric J. Crabill
  • Patent number: 7421517
    Abstract: A method according to one embodiment may include operating an integrated circuit in a selected mode of operation. The integrated circuit may include processor circuitry and interface circuitry. The processor circuitry may include a plurality of processor cores. The interface circuitry may be capable of communicating in accordance a plurality of different protocols. At least one of the processor cores may be capable of issuing a command to the interface circuitry to communicate in accordance with at least one of the plurality of different protocols that corresponds to the selected mode of operation of the integrated circuit.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: September 2, 2008
    Assignee: Intel Corporation
    Inventors: Richard C. Beckett, Deif N. Atallah
  • Patent number: 7401205
    Abstract: A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: July 15, 2008
    Assignee: MIPS Technologies, Inc.
    Inventors: William J. Dally, W. Patrick Hays, Robert Gelinas, Sol Katzman, Sam Rosen, Staffan Ericsson
  • Patent number: 7249246
    Abstract: Methods and systems that allow recovery of the program counter or instruction pointer for a target (non-native) instruction that is translated into a host (native) instruction, and that allow recovery of other information about the translator or the target system state, are described. The program counter or instruction pointer can be recovered, for example, after an exception has been processed or incident to a rollback operation.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: July 24, 2007
    Assignee: Transmeta Corporation
    Inventors: John P. Banning, H. Peter Anvin, Guillermo J. Rozas
  • Patent number: 7234042
    Abstract: An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent operations. The instruction includes designated bits at predetermined bit locations which identify whether the instruction is a long instruction or a dual operation instruction.
    Type: Grant
    Filed: September 13, 1999
    Date of Patent: June 19, 2007
    Assignee: Broadcom Corporation
    Inventor: Sophie Wilson
  • Patent number: 7216185
    Abstract: Buffer control means and output control means are included within a buffering apparatus. Data longer than the width of data bus is read by single access from buffer means. Rather than signal line control for each bus width, signal line control for each data group is performed by a method wherein address administration means holds address information in relationship with each group of a series of data written in the buffer means and data is output from the buffer means.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: May 8, 2007
    Assignee: NEC Corporation
    Inventor: Tetsuya Kato
  • Patent number: 7206882
    Abstract: A CANOpen network including a bus master and an I/O module is disclosed. Each is communicatively coupled to a common bus. The I/O module is subject to a state change. The bus master collects state information from the I/O module by determining if the bus master is prepared to receive further data from the bus and sending a trigger signal from the bus master to the I/O module if the bus master is prepared to receive further data from the bus. The I/O modules sends a state signal to the bus master in response to the trigger signal.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: April 17, 2007
    Assignee: Schneider Automation Inc.
    Inventors: William A. White, III, Lawrence W. Hill, James McLean, William D. Sparks, Jean Francis Rolland
  • Patent number: 7206871
    Abstract: An extending circuit for memory includes an output data effective signal generator for, when a status signal from a next-stage FIFO circuit represents a data writable state, asserting a write enable signal from the next-stage FIFO circuit, and enabling data to be written into the next-stage FIFO circuit. The extending circuit for memory also includes an internal FIFO write enable generator for receiving a status signal from the next-stage FIFO circuit, asserting an internal FIFO write enable signal, and enabling data to be written into an internal FIFO circuit of the extending circuit for memory, when the next-stage FIFO circuit is in a data unwritable state.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 17, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hiroyasu Noda
  • Patent number: 7203775
    Abstract: A system and method avoids deadlock, such as circular routing deadlock, in a computer system by providing a virtual buffer at main memory. The computer system has an interconnection network that couples a plurality of processors having access to main memory. The interconnection network includes one or more routing agents each having at least one buffer for storing packets that are to be forwarded. When the routing agent's buffer becomes full, thereby preventing it from accepting any additional packets, the routing agent transfers at least one packet into the virtual buffer. By transferring a packet out of the buffer, the routing agent frees up space allowing it to accept a new packet. If the newly accepted packet also results in the buffer becoming full, another packet is transferred into the virtual buffer. This process is repeated until the deadlock condition is resolved. Packets are then retrieved from the virtual buffer.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: April 10, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory E. Tierney
  • Patent number: 7203795
    Abstract: A recording/reproducing apparatus for recording a received signal as digital data in a file format and for reproducing the digital data stored in the file format includes a memory controller which controls the recording made in a manner such that the digital data continuously received and stored in a buffer memory is stored in a storage unit at a writing speed which is higher than a speed at which the digital data is stored in the buffer memory. In a reproducing mode, the digital data is read from the storage unit into the buffer memory at a reading speed which is higher than a speed at which the digital data is outputted from the buffer memory to the outside.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: April 10, 2007
    Assignee: D & M Holdings Inc.
    Inventor: Mitsuhiro Urazoe
  • Patent number: 7200697
    Abstract: A method and apparatus for transferring data between storage systems including a first disk system for receiving first data in a variable length data format from a host, storing the first data and sending the first data over an I/O channel for data in the variable length data format, a second storage system for receiving the first data from the first storage system, converting the first data from the first storage system to second data in a fixed block data format and sending the second data over an I/O channel for data in the fixed block data format, and a third storage system for receiving the second data from the second storage system, converting the second data from the second storage system back to the first data and storing the first data.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: April 3, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Akira Yamamoto, Kenji Yamagami
  • Patent number: 7200689
    Abstract: A method and an apparatus are provided for loading data to a local store of a processor in a computer system having a direct memory access (DMA) mechanism. A transfer of data is performed from a system memory of the computer system to the local store. The data is fetched from the system memory to a cache of the processor. A DMA load request is issued to request data. It is determined whether the requested data is found in the cache. Upon a determination that the requested data is found in the cache, the requested data is loaded directly from the cache to the local store.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: April 3, 2007
    Assignee: International Business Machines Corporation
    Inventor: James Allan Kahle
  • Patent number: 7197630
    Abstract: A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional branch operation stored in an entry of a trace cache, and in response to predicting the execution path, if a first operation stored in the entry of the trace cache is not in the execution path according to the prediction, assigning to the first operation a non-executable status indicative that the first operation is not in the execution path. The method may further include detecting that the prediction is incorrect subsequent to assigning the non-executable status to the first operation and assigning an executable status to the first operation in response to detecting the incorrect prediction, where the executable status is indicative that the first operation is in the execution path.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 27, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mitchell Alsup, Benjamin T. Sander
  • Patent number: 7197577
    Abstract: The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to job requests submitted by processes in the computer system are monitored and analysed. These heuristics may include the number of read and write requests, the ratio of read requests to write requests, input/output throughput, disk utilization and the average time taken for processes to submit subsequent jobs once an initial job completes. The analysed heuristics are compared to the desired sets of heuristics for the plurality of input/output schedulers to select one of the plurality of input/output schedulers.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: March 27, 2007
    Assignee: International Business Machines Corporation
    Inventor: Hariprasad Nellitheertha
  • Patent number: 7197583
    Abstract: The present invention provides an SDIO controller, an SDIO wireless communication card, an SDIO wireless communications module, and a method for transmitting write data from an SDIO host device to an SDIO application. Specifically, the SDIO controller is a single-chip semiconductor device connecting an SDIO-compliant SDIO host device with a plurality of applications via an SD bus, wherein the controller includes: (a) an SD interface operably connectable with the SDIO host device to decode commands received from the SDIO host device, and to return a response to the SDIO host device; (b) one or more application interfaces; and (c) a temporary memory operably connected between the SD interface and the one or more application interfaces.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: March 27, 2007
    Assignee: Zentek Technology Japan, Inc.
    Inventors: Jun Takinosawa, Hiroyuki Yasoshima
  • Patent number: 7197581
    Abstract: The integrated circuit comprises, in addition to a first bus and a first DMA controller, a second bus and a second DMA controller that mutually connects the first bus and the second bus. A main memory is connected to the first bus, and a frame memory is connected to the second bus. By the construction, a possible conflict in data transfer as “urgent processing” and as “normal processing” can be avoided. The data transfer as “urgent processing” includes transferring image data between the frame memory and an image input device or an image display device; while the data transfer as “normal processing” includes transferring image data between the main memory and the frame memory.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: March 27, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yasuo Kohashi
  • Patent number: 7197627
    Abstract: A processing arrangement for a computer comprising: first processor means (1) for processing a first set of instructions; and second processor means (2) for processing a second set of instructions, the second set of instructions being a subset of the first set of instructions, wherein the second processor means (2) is arranged to receive control signals and to process instructions in dependence upon those control signals without reference to the first processor means.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: March 27, 2007
    Assignee: Telefonaktoebolaget LM Ericsson (publ)
    Inventor: Rowan Nigel Naylor