Patents Examined by Fritz Fleming
  • Patent number: 7134094
    Abstract: Automatic assignment of shortcut keys for launching applications or for providing other commands is provided based on the position of corresponding application listings or shortcuts in a menu. The menu may include an applications menu, such as a start menu. The menu may also include an application launch bar listing applications that may be launched therefrom by selecting the respective application, or by entering shortcut keys that are automatically assigned based on the position of the application listing on the launch bar. Methods are provided for assigning application launch shortcut keys, for identifying assigned shortcut keys, for modifying shortcut keys, and for using shortcut keys for instantiating or switching applications.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 7, 2006
    Assignee: Microsoft Corporation
    Inventors: Charles W. Stabb, David A. Matthews, Sarah E. Schrock
  • Patent number: 7130937
    Abstract: In a method for providing a video data streaming service, a server determines whether an occupancy is below a first threshold or is equal to or greater than a second threshold, the occupancy representing the amount of data occupying a queuing buffer of a terminal and the first threshold being less than the second threshold. If the occupancy is not below the first threshold, the server provides the data streaming service at a predetermined service bit rate which is less than the current service bit rate. If the occupancy is equal to or greater than a second threshold, the server provides the data streaming service at a predetermined service bit rate which is greater than the current service bit rate.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: October 31, 2006
    Assignee: SK Telecom Co., Ltd.
    Inventors: In Seong Hwang, Sang Ho Chae, Hee Won Park, Keun Hee Shin, Chang Ho Choi, Won Hee Sull
  • Patent number: 7130926
    Abstract: Label information used by a downstream LSR is mirrored on an upstream LSR. In particular, a copy of the label information database in the downstream LSR from LDP sessions is stored on the upstream LSR. The label information database and corresponding mirror are synchronized. The mirror is employed to facilitate recovery from control plane failure through comparison of the label information database with the mirror. For example, the intersection of the label information database and the mirror may be calculated and employed as the updated label information database and mirror.
    Type: Grant
    Filed: June 25, 2001
    Date of Patent: October 31, 2006
    Assignee: Nortel Networks Limited
    Inventors: Jing Wu, Delfin Y. Montuno, Guoqiang Wang
  • Patent number: 7130928
    Abstract: A processing apparatus which stores a first information piece about attributes identifying a specific process generating data input/output requests in such a manner that the first information piece is associated with a second information piece identifying at least one of the physical paths as at least one first physical path, and which, when transmitting first data input/output requests generated by the process identified by the first information piece to the storage apparatus, transmits the first data input/output requests to the storage apparatus via the first physical path identified by the second information piece associated with the first information piece and, when transmitting second data input/output requests generated by a process not identified by the first information piece to the storage apparatus, transmits the second data input/output requests to the storage apparatus via at least one second physical path different from the first physical path of the plurality of physical paths.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: October 31, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Hayashi, Hiroshi Morishima, Osamu Kohama
  • Patent number: 7127534
    Abstract: A method for managing read and write data congestion in a system for executing write and read data commands and having a buffer pool of blocks for temporarily storing read and write data is disclosed. Management of the buffer pool and the initiation of read and write commands ensures that free blocks are available to temporarily store read data arriving at a host bus adapter (HBA). If the currently available blocks would be substantially consumed by the total outstanding inbound read data requested, no more write data commands will be initiated. As inbound read data is received into the buffer pool and subsequently transferred out of the buffer pool to the initiator device, the blocks in the buffer pool are freed up. When the read data transfer is completed and sufficient buffer resources have been freed up, read and write data commands may resume.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: October 24, 2006
    Assignee: Emulex Design & Manufacturing Corporation
    Inventors: Thomas Patrick Jackson, Curtis Edward Nottberg, David Robert Wiley, Marc Timothy Jones
  • Patent number: 7127529
    Abstract: A smart card comprises a microcontroller, a memory unit, a storage unit, and a communications unit. The smart card may be connected to a terminal, which is in turn may be connected to a host computer and/or a network. The smart card is configured to initiate communications with the terminal, which enables the smart card to control the terminal, host computer, or network and to access the resources connected to the terminal, host computer, or network. A communications protocol defines the commands that the smart card can send and allows the smart card to communicate using asynchronous or logical asynchronous communication.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: October 24, 2006
    Assignee: AxAlto, Inc.
    Inventors: Michael A. Montgomery, Scott B. Guthery, Bertrand du Castel
  • Patent number: 7124214
    Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: October 17, 2006
    Assignee: VIA Technologies Inc.
    Inventors: Jiin Lai, Chad Tsai, Ju Zhang, Andrew Chuang, Andrew Su
  • Patent number: 7124211
    Abstract: Embodiments of the invention include a mechanism for explicit communication in a clustered multiprocessor system that supports low-latency, protected, user-mode, communication across the machine boundaries of a clustered multiprocessor. Data transport may be accomplished over persistent, unidirectional, point-to point connections, each of which may be embodied in a small amount of state at each end, along with a statically allocated per-connection memory buffer, which may be directly accessible to the transport mechanism at both ends of each notional link. System Memory protection may be afforded by operating system (“OS”) facilitated allocation of both restricted control of the network interface, and responsibility for data transport, to an application thread that may execute in the context of the processor-managed virtual address space. Connection buffer protection may be afforded by restricting access to connection state to those entries associated with the currently controlling thread.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: October 17, 2006
    Assignee: SRC Computers, Inc.
    Inventors: Christopher Dickson, David Caliga, James O'Connor, Daniel Poznanovic
  • Patent number: 7120783
    Abstract: A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 10, 2006
    Assignee: Ubicom, Inc.
    Inventors: David A. Fotland, Tibet Mimaroglu
  • Patent number: 7120708
    Abstract: Apparatus and method for carrying out a DMA transfer wherein an address is written into a DMA register of a DMA controller specifying a memory location within a memory device at which either the parameters for a transfer of a block of data are provided or the status of the transfer of a block of data is to be written by the DMA controller.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: William T. Futral, Jie Ni
  • Patent number: 7120679
    Abstract: An arrangement is provided for configuring a headless device. A self-initiated configuration mechanism within a headless device issues a configuration request to a configuration service mechanism across network, requesting a configuration specification corresponding to the headless device. The configuration service mechanism returns the requested configuration specification to the self-initiated configuration mechanism. Upon receiving the configuration specification, the self-initiated configuration mechanism configures the headless device according to the configuration specification.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventor: Eric B. Remer
  • Patent number: 7117278
    Abstract: A method of merging a first data stream with a second data stream to generate a third data stream. The method comprises receiving a first packet from the first data stream, the first packet containing a first packet ID and a first data payload and receiving a second packet from the second data stream, the second packet containing a second packet ID and a second data payload. The method also includes storing first data in a plurality of packet ID arrival registers, a first portion of the first data indicating that the first packet ID is equal to the ID associated with a first of the plurality of the packet ID arrival registers and storing second data in the plurality of packet ID arrival registers, a first portion of the second data indicating that the second packet ID is equal to the ID associated with the second of the plurality of the packet ID arrival registers.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: October 3, 2006
    Assignee: Sun Micro Systems, Inc.
    Inventor: James M. Avery
  • Patent number: 7114014
    Abstract: Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: September 26, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael Yatziv, Satyanarayana Nishtala, Whay Sing Lee, Raghavendra J. Rao
  • Patent number: 7114010
    Abstract: Techniques for controlling and managing network access are used to enable a wireless communication device to selectively communicate with several wireless networks. A portable communication device constructed according to the invention can communicate with different networks as the device is moved through the areas of coverage supported by the different networks. As a result, the device can take advantage of services provided by a particular network when the device is within the area of coverage provided by that network. Thus, the device can selectively switch to networks that provide, for example, high speed Internet access, different quality of service, low cost service and/or different services (e.g., voice, data, multimedia, etc.). A multi-mode controller in the device may be used to alternately poll different networks to determine whether the device is within the area of coverage of a network and to selectively establish communications with those networks.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: September 26, 2006
    Assignee: Broadcom Corporation
    Inventors: Jeyhan Karaoguz, Nambi Seshadri
  • Patent number: 7114059
    Abstract: System and method to reduce execution of instructions involving unreliable data in a speculative processor. A method comprises identifying scratch values generated during speculative execution of a processor, and setting at least one tag associated with at least one data area of the processor to indicate that the data area holds a scratch value. Such data areas include registers, predicates, flags, and the like. Instructions may also be similarly tagged. The method may be executed by an execution engine in a computer processor.
    Type: Grant
    Filed: November 5, 2001
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventor: Christopher B. Wilkerson
  • Patent number: 7114017
    Abstract: A peripheral switch (62) is electrically interposed between a peripheral device (10) and a plurality of computing devices respectively coupled to host computer ports (70a)–(70N). The peripheral switch (62) includes host computer port state sensing means (110) for determining a state of each host computer port (70a)–(70N) and providing a communication path to the peripheral device (10) from a host computer port (70a)–(70N) at a state indicative of a server computer being coupled thereto. The peripheral switch (62) further includes local handshaking means (120) for simulating communications from a server computer to peripheral device (10) if none of host computer ports (70a)–(70N) are determined to be coupled to a server computer.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: September 26, 2006
    Assignee: The Mitre Corporation
    Inventor: Donald L. Parrish
  • Patent number: 7111088
    Abstract: To provide an computer system including a storage system that includes a logical device logically set in a physical device, an host computer that requests the storage system for a data input/output, and a management device that manages information of components of the storage system, the host computer requesting a data input/output via a logical path serving as a communication paths with the logical device and, the some of the host computer restricted to send the data input/output request to the logical device, wherein the management device includes an information acquisition module that acquires the information of the components in the storage system, and a judging module that selects a logical device to move based on a number of logical paths set on the logical devices and a number of communication counterpart devices set through effective logical paths in the information acquired by the information acquisition module.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 19, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Naoto Kawasaki, Yasufumi Uchiyama
  • Patent number: 7111084
    Abstract: A method and host bus adapter for controlling failover and failback processes within a redundant data storage system. The method is carried out by a failover mechanism in a host bus adapter linked to a host server. The system includes a communication fabric providing data paths to pairs of redundant storage controllers managing access to storage devices (such as hard disk drives arranged as RAID). The method includes operating the host bus adapter to detect a failover condition and in response, to match the failover condition to a particular failover action. The failover conditions and corresponding actions are stored in a well-defined rule set accessed by the host bus adapter. The method continues with performing with the host bus adapter the matched failover action. The method is transparent to the host computer device, as the host is not required to participate in the failover processes.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 19, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Choon-Seng Tan, Michael D. White, Greg J. Pellegrino
  • Patent number: 7111093
    Abstract: According to some embodiments, a ping-pong buffer system has a buffer that stores a subset of data from a data source.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: September 19, 2006
    Assignee: Intel Corporation
    Inventors: Muraleedhara Navada, Sreenath Kurupati
  • Patent number: 7111080
    Abstract: Techniques are provided for distributing signals in a stackable unit, including a first input connector of two or more input connectors; a second input connector of two or more input connectors, wherein the first input connector is spaced apart from the second input connector, and the first input connector has a particular spatial relationship to the second input connector; a first output connector of two or more output connectors; a second output connector of two or more output connectors, wherein the first output connector is spaced apart from the second output connector, and the first output connector has the same particular spatial relationship to the second output connector; means for communicatively coupling the first input connector and the second output connector; and means for terminating the first output connector.
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: September 19, 2006
    Assignee: Cisco Technology, Inc.
    Inventor: Bruce Moon