Patents Examined by Fritz Fleming
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Patent number: 7149793Abstract: The invention is concerned with a method in a communication network for invoking services, the communication network including at least one or more terminals and at least two service entities. In the method the terminal deduces necessary support and service components for providing an end-user service. A set of configuration requests is constructed at the terminal, each associated with one or more specific service entities for invoking individual service components composing a service. Each configuration request is forwarded from the terminal to the service entity/entities indirectly, by using a special network support function for configuring service entities—the assembler unit of the invention—or directly in a way, which is chosen in accordance with pre-defined criteria. The invention is also concerned with a communication network, a terminal and an assembler unit to perform the method.Type: GrantFiled: May 26, 2005Date of Patent: December 12, 2006Assignee: Telefonaktiebolaget LM Ericsson (publ)Inventors: Göran Eriksson, Jan Höller
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Patent number: 7149879Abstract: A processor and method of automatic instruction mode switching between N-bit and 2N-bit instructions by using parity bit check. The processor and method includes an instruction input device having a memory for storing a plurality of 2N-bit words, an instruction fetch device fetching a 2N-bit word from the memory, and a mode switch logic determining whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction to accordingly switch the processor to corresponding N-bit or 2N-bit mode, wherein when the 2N-bit word fetched is even parity, the 2N-bit word is determined as two (N-P)-bit instructions if two N-bit words included in the 2N-bit word are on the even parity state, or determined as a 2(N-P)-bit instruction if the two N-bit words are on the odd parity state.Type: GrantFiled: October 14, 2003Date of Patent: December 12, 2006Assignee: Sunplus Technology Co., Ltd.Inventor: Bor-Sung Liang
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Patent number: 7146439Abstract: A scheduling method and apparatus for use by a processor that controls storage devices of a data storage system is presented. The method allocates processing time between I/O operations and background operations for predetermined time slots based on an indicator of processor workload.Type: GrantFiled: June 27, 2003Date of Patent: December 5, 2006Assignee: EMC CorporationInventors: Adi Ofer, Daniel E. Rabinovich, Stephen R. Ives, Peng Yin, Cynthia J. Burns, Ran Margalit, Rong Yu
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Patent number: 7146438Abstract: In a device and method for controlling packet flow, priority data of a packet received by one of a plurality of ports are determined. A packet memory is monitored to determine whether an address pointer of the packet memory exceeds a predetermined limit value. A port is selected to control packet flow by using the priority data when the address pointer of the packet memory exceeds the predetermined limit value. Then, the selected port is directed to control the packet flow. By using the priority data designated to a packet or a port, the packet flow may be controlled in consideration of various kinds of network services.Type: GrantFiled: October 28, 2003Date of Patent: December 5, 2006Assignee: Samsung Electronics Co., Ltd.Inventor: Kyu-Wook Han
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Patent number: 7146486Abstract: A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality of successive, adjacent time intervals. Each unit provides an output data item in the time interval in which the unit performs the operation and provides a processed data item in the last of the successive, adjacent time intervals. The special function unit provides a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs the operation, so as to avoid a conflict in use among the scalar units. A vector processing unit includes an input data buffer, the scalar processor, and an output orthogonal converter.Type: GrantFiled: January 29, 2003Date of Patent: December 5, 2006Assignee: S3 Graphics Co., Ltd.Inventors: Boris Prokopenko, Timour Paltashev, Derek Gladding
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Patent number: 7146445Abstract: A test apparatus for telecommunication equipment includes motherboard that executes a resident operation control mechanism, so that the test apparatus exhibits default hardware functionality. However, if a daughtercard has been plugged into the motherboard, the motherboard ignores the default firmware and executes whatever replacement operation control software is provided on the daughtercard—causing the test apparatus to acquire a hardware functionality exclusive of the motherboard default.Type: GrantFiled: January 23, 2004Date of Patent: December 5, 2006Assignee: Adtran, Inc.Inventors: Robert Scott Appleton, Patrick Steven Grant, David Etzkorn
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Patent number: 7143203Abstract: It has been discovered that system operational characteristics (e.g., power level, clock frequency, processor utilization, operating system time slice utilization, size and age of queued jobs) may be used to predict storage access requirements for the system. By predicting the storage access requirements of a system, a storage subsystem may be advantageously controlled to anticipate storage accesses. A storage device or array of such devices can be configured to operate, for example, at selected speeds no greater than that required to process the predicted storage access requirements. The storage access prediction may be based, for example, on the frequency and voltage at which a processor is running or based on other system performance indicators such as job backlog and age and size thereof. Various controllable characteristics such as the speed of a hard drive's storage media, the current applied to a read/write head, etc.Type: GrantFiled: April 26, 2002Date of Patent: November 28, 2006Assignee: Advanced Micro Devices, Inc.Inventor: Morrie Altmejd
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Patent number: 7143209Abstract: A storage control apparatus concatenates a plurality of logical units to construct a large capacity logical unit, wherein logical units extending over a plurality of controllers can be concatenated. The channel adapter sends an I/O request to one controller which charges one logical unit constituting the concatenation logical unit, out of a plurality of controllers when an I/O request is sent from a host to the concatenation logical unit LU linking a plurality of logical units, executes I/O processing in the one controller, then sends the I/O request to another controller which charges another logical unit constituting the concatenation logical unit, and continues I/O processing in the another controller.Type: GrantFiled: January 29, 2004Date of Patent: November 28, 2006Assignee: Fujitsu LimitedInventors: Koji Uchida, Takaaki Saito, Mikio Ito, Kazuma Takatsu, Hidejirou Daikokuya, Akihito Kobayashi, Kazuhiko Ikeuchi, Sanae Kamakura, Shinichi Nishizono
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Patent number: 7143198Abstract: A network connection state can be conveniently changed to a wired or a wireless connection state according to whether a portable computer body is attached to a docking station including an Access Point part or not.Type: GrantFiled: October 7, 2003Date of Patent: November 28, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Cheon-moo Lee, Il-han Lee
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Patent number: 7143267Abstract: A method and multithreaded processor for dynamically reallocating prefetch registers upon the processor switching modes of operation. An execution unit may be coupled to a prefetch engine where the execution unit may be configured to receive prefetch instructions regarding prefetching data. The prefetch engine may comprise a plurality of prefetch registers. The execution unit may further be configured to load the plurality of prefetch registers with information regarding prefetching data obtained from the prefetch instructions. In a single thread mode of operation, the plurality of prefetch registers are allocated to be accessed by either a first or a second thread. In a multithread mode of operation, the plurality of prefetch registers are allocated to be accessed among the first and second threads.Type: GrantFiled: April 28, 2003Date of Patent: November 28, 2006Assignee: International Business Machines CorporationInventors: Eric J. Fluhr, Cathy May, Balaram Sinharoy
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Patent number: 7143269Abstract: An apparatus for killing an instruction after it has already been loaded into an instruction queue of a microprocessor is disclosed. The apparatus includes control logic that detects a condition in which the instruction must not be executed, such as a branch instruction misprediction; however, the control logic determines the condition too late to prevent the instruction from being loaded into the instruction queue. The control logic generates a kill signal indicating the instruction must not be executed. A kill queue receives the kill signal and stores its value. The kill queue maintains its entries in parallel with the instruction queue entries so that when the instruction queue subsequently outputs the instruction, the kill queue also outputs the value of the kill signal associated with the, instruction. If the kill signal value output from the kill queue is true, then the microprocessor invalidates the instruction and does not execute it.Type: GrantFiled: July 31, 2003Date of Patent: November 28, 2006Assignee: IP-First, LLCInventor: Thomas McDonald
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Patent number: 7139851Abstract: A method and apparatus for re-synchronizing a remote mirroring pair including first and second storage systems which are connected to each other via a path, the first storage system being connected to a host. A primary volume is provided to the first storage system and a remote secondary volume is provided to the second storage system. The remote secondary volume is a copied volume of the primary volume which is in synchronous mode with the remote secondary volume. A local secondary volume is provided in the first storage system and has stored therein journal logs of write I/O's from the host and old data including write data of previous write I/O's. Recovery of data on the primary volume based on the local secondary volume is conducted when necessary by applying the journal logs to the old data without suspending the synchronous mode between the primary and remote secondary volumes.Type: GrantFiled: February 25, 2004Date of Patent: November 21, 2006Assignee: Hitachi, Ltd.Inventor: Akira Fujibayashi
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Patent number: 7139845Abstract: The snapshot capability moving into the SAN fabric and being provided as a snapshot service. A well-known address is utilized to receive snapshot commands. Each switch in the fabric connected to a host contains a front end or service interface to receive the snapshot command. Each switch of the fabric connected to a storage device used in the snapshot process contains a write interceptor module which cooperates with hardware in the switch to capture any write operations which would occur to the snapshot data area. The write interceptor then holds these particular write operations until the original blocks are transferred to a snapshot or separate area so that the original read data is maintained. Should a read operation occur to the snapshot device and the original data from requested location has been relocated, a snapshot server captures these commands and redirects the read operation to occur from the snapshot area.Type: GrantFiled: April 29, 2003Date of Patent: November 21, 2006Assignee: Brocade Communications Systems, Inc.Inventors: Balakumar N. Kaushik, Shankar Balasubramanian, Richard L. Hammons
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Patent number: 7139817Abstract: The invention provides for managing information for multiple devices. Each of a set of devices retrieves information from a sequence of servers. A device when starting up reads a list of file names, reads information from each file in sequence, and resolves conflicts among files to present a consistent configuration on each restart of each device. A file includes a sequence of <name, value> pairs. In those cases when two variables have the same name, an operator associated with the second pair indicates whether to overwrite the first value or to edit the first value, such as by appending the second value. One of the pairs indicates the list of file names itself. When the list of file names is changed, the device for which the change is made re-reads the sequence of files and repeats its determination of the pairs, until the list of file names is stabilized.Type: GrantFiled: June 12, 2001Date of Patent: November 21, 2006Assignee: Network Appliance, Inc.Inventors: Robert M. English, Szu-Wen Kuo, Brian Quirion
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Patent number: 7136940Abstract: An Internet refrigerator with a Web pad and a method for operating the same. The Web pad is detachably mounted on the Internet refrigerator, and transmits and receives data to/from the Internet refrigerator on the basis of a remote display protocol (RDP). The Web pad is a client Web pad detachably mounted on an outer surface of the Internet refrigerator. The client Web pad is adapted to receive a display signal transmitted from the Internet refrigerator and output the received display signal externally. A server control unit is provided to transmit the display signal to the client Web pad on the basis of the remote display protocol such that data processed in the Internet refrigerator is displayed through the client Web pad. Application programs and multimedia data are driven on the basis of the server control unit, resulting in a reduction in work-load on the client Web pad.Type: GrantFiled: November 6, 2003Date of Patent: November 14, 2006Assignee: LG Electronics Inc.Inventors: Young Hoon Roh, Jung Ho Kim, Jin Cheol Cho, Jae Won Chang, Sang Hyuk Kang, Sang Mahn Kim, Pan Su Kim
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Patent number: 7136939Abstract: Configuration information settings for a storage device are made highly reliable and facilitated. The storage device includes a service processor for setting storage device configuration information, and a terminal device connected to the service processor via a private line to send a command group, received from an operator and related to the storage device configuration information, to the service processor. The service processor also includes a device for determining approval or denial of execution of the command group prior to execution of the command group received from the terminal device.Type: GrantFiled: August 5, 2003Date of Patent: November 14, 2006Assignee: Hitachi, Ltd.Inventors: Toshimichi Kishimoto, Yoshinori Igarashi, Shuichi Yagi
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Patent number: 7136943Abstract: A method, apparatus and computer instructions for storing data relating to the switch in a context switch history containing a number of prior context switches occurring prior to a current context. The storing of data occurs in response to a change in context for a direct memory access resource. Portions of the direct memory access chain of requests are freed using the context switch history to form freed portions, wherein the freed portions are reused for requests.Type: GrantFiled: March 18, 2004Date of Patent: November 14, 2006Assignee: International Business Machines CorporationInventors: Wei Kuo, James A. Pafumi, Robert Paul Stelzer
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Patent number: 7134002Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.Type: GrantFiled: August 29, 2001Date of Patent: November 7, 2006Assignee: Intel CorporationInventor: Ken Shoemaker
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Patent number: 7134005Abstract: A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and is present in a cache line of instruction bytes provided by an instruction cache in response to a fetch address, a target address of the branch instruction, and a location of an opcode byte of the branch instruction within the cache line. The instruction cache provides the cache line to an instruction buffer and the BTAC provides the prediction, the target address, and the location in response to the fetch address. The microprocessor branches to the target address. A byte in the cache line within the instruction buffer indicated by the location provided by the BTAC is marked. An instruction decoder formats the instruction bytes in the cache line.Type: GrantFiled: May 4, 2001Date of Patent: November 7, 2006Assignee: IP-First, LLCInventors: G. Glenn Henry, Thomas C. McDonald, Terry Parks
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Patent number: 7133906Abstract: The invention provides a system for remotely configuring a plurality of devices to customize a lab network system for testing components and for training operators to use and maintain such systems. The system is configured to remotely access and control such a system via a computer network such as the Internet. Once connected, a user can run testing scenarios on the configured devices remotely from any location that has access to the Internet. In accordance with the invention, an organization's network equipment is integrated with specialized physical switching technologies, and controlled by unique management software. Access to the network equipment may be provided remotely, and granted via a scheduling service. Thus, multiple physical equipment labs can be integrated into one globally, visible resource, enabling one-stop scheduling of lab time without knowing the detailed inventory of a particular network equipment facility.Type: GrantFiled: February 16, 2001Date of Patent: November 7, 2006Assignee: Lumenare NetworksInventors: Chuck Price, Kelley Stover, Thomas Suplica, Curtis Bray, Mary Rygaard, Ben Tsao