Abstract: A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.

Abstract: Disclosed is a disk control apparatus with excellent scalability realized on the same architecture, in high quality and reliability, regardless of its scale. Each of a plurality of channel interface units and a cache memory unit as well as each of a plurality of disk interface units and the cache memory unit are connected through a switch and a data path network (solid line) in each disk control cluster. Each switch provided outside each disk control cluster is connected to the switch in each disk control cluster through the data path network. A resource management unit is provided outside each disk control cluster and the resource management unit is connected to each of the plurality of channel interface units/disk interface units, as well as to the cache memory unit in each disk control cluster. The resource management unit is also connected to each switch provided outside each disk control cluster through a resource management network (dotted line).

Abstract: A system and a method for changing the communication means used for communication between two software agents. Each software agent has a communication module, which gives the software agents access to the communication means. In addition, the software agents have means for receiving a new communication module from the communication server.

Abstract: A system and method for using a conventional, unmodified operating system that routinely issues disk I/O requests in a diskless network computer. An adapter receives the disk I/O requests and translates them to network I/O requests, transparently to the CPU. The requests are satisfied using the network. In this way, the operating system need not be modified to issue network calls instead of disk requests.

Abstract: The invention describes a modification of FIFO hardware to allow improved use of FIFOs for burst reading from or writing to a processor direct memory access unit via either an expansion bus or an external memory interface using FIFO flag initiated bursts. The hardware and FIFO signal modifications make the FIFO-DMA interface immune to deadlock conditions and generation of spurious interrupt events in the process of initiating burst transfers. The FIFO function is modified to synchronize the frame transfer on the digital signal processor even if the digital signal processor lacks this functionality. By delaying the programmable flag assertions within the FIFO until after the current burst is complete the DSP-FIFO interface may be made immune to deadlock conditions and generation of spurious events.

Abstract: A rotary multi-tooth milling cutter, each tooth having a tooth face is provided. The tooth face has at least two sections, a first section nearest the cutting edge having a convex form as viewed in a cross section perpendicular to the cutter axis and a second section in a concave form.

Abstract: A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by a word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit.

Abstract: Methods, systems, and devices are provided for a media platform. One method includes receiving DMA requests for connecting media data traffic to DMA slots of a DMA memory module. Available DMA slots are determined from a pool of available DMA slots and allocated for media data traffic. DMA slots are released to the pool of available DMA slots when a DMA slot is no longer being used. The method further includes using a TMC proxy to connect media data traffic between the DMA memory module and a DSP software module based on assigned DMA slots.

Abstract: A device is presented including a host controller capable of attaching a quantity of queue heads to a frame list. The quantity of queue heads are attached to the frame list before any transaction descriptors where split-isochronous transaction descriptors are supported.

Abstract: A generic quality of service (“G-QoS”) protocol and architecture for applications executing in multiple transport protocol environments is provided. G-QoS negotiators establish a QoS level for user applications by communicating over a network and exchanging network and application data via a G-QoS protocol that can be implemented using out-of-band ICMP messages. A Dynamic Profile Management Algorithm (“DPMA”) allows the G-QoS negotiators to negotiate, establish, and maintain the desired QoS level between the user applications by providing real-time monitoring of application parameters including bandwith, buffer, and cache status information of the communicating client and server. A G-QoS applications programmer interface (“API”) allows network administrators to easily monitor and maintain the overall G-QoS architecture of the present invention. The G-QoS negotiators, G-QoS protocol, and DPMA form a generic QoS architecture that provides guaranteed QoS for user applications.

Abstract: In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also configured to monitor for a plurality of conditions for each thread, wherein each of the plurality of conditions defined to inhibit the thread from being fetched. The fetch generator circuit is configured to speculatively generate a first fetch request for a first thread of the plurality of threads if each thread is inhibited from fetching and the first thread is inhibited from fetching only due to a first predetermined condition of the plurality of conditions. In one particular implementation, the first predetermined condition is a lack of room in a corresponding one of a plurality of instruction buffers.

Abstract: An apparatus for avoiding a deadlock condition in a microprocessor with a speculative branch target address cache (BTAC) that predicts a target address of a branch instruction contained in a cache line output by an instruction cache in response to a fetch address is disclosed. The BTAC incorrectly predicts the branch instruction is wholly contained in the cache line; consequently, the microprocessor fetches from the target address without fetching the next sequential cache line containing the rest of the instruction. An instruction formatter detects the instruction is only partially contained in the cache line and waits for the next cache line. However, the formatter receives no more cache lines because the target address misses in the cache and the missing cache line is not fetched from memory because the processor does not generate speculative instruction fetches. To avoid deadlocking, the apparatus invalidates the BTAC target address and retries.

Abstract: In a processing core, a newly received load instruction may be dependent upon a previously received store instruction. The core may include a predictor to predict such dependencies and provide an identification of a colliding store instruction. The load instruction may be stored in a scheduler with a dependency marker. Thereafter, the load instruction may be prevented from executing until after execution of the colliding store. Upon execution of the load, the accuracy of the prediction is confirmed. Upon retirement of the load instruction, new prediction results may be provided to the predictor.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. The performance indicators and counter values may be used as a mechanism for identifying cache hits and cache misses. Performance counters are incremented each time the instructions of routines of interest are executed and each time the instructions must be reloaded into the cache. From the values of these counters the cache hit-miss ratio may be determined. When the cache hit-miss ratio becomes less than a predetermined threshold, i.e. a greater number of cache misses than cache hits, the present invention may determine that a problem condition has occurred and initiate “chase tail” operations for avoiding overwriting of entries in the cache.

Abstract: A REPEAT instruction for repeated execution of an associated instruction (INSTR). Once a program counter stores the address for the instruction to be repeated, it remains unchanged until the associated instruction (INSTR) has been executed the number of times indicated by a COUNT value in a preloaded register, or alternatively, by the REPEAT instruction itself. In this manner, the present invention reduces the number of instruction fetches required to repeatedly execute the associated instruction (INSTR). Consequently, there is a significant improvement in the efficiency of the program code execution.

Abstract: A queue monitoring system and method determines when one or more transmit queues have reached a state that requires action by the host processing device, without the need for periodic polling of transmit status or excessive interrupt servicing. The queue monitoring implements an interrupt mechanism that generates an interrupt if one or more of the transmit queues has gone from a non-empty state to an empty state, and remained in the empty state for a (programmable) period of time. The combination of queue status checking (when adding new transmit data) with the queue monitoring interrupt mechanism removes the need for periodic polling of queue status and handling of interrupts generation on the completed transmission of data from one or more transmit buffer.

Abstract: An arrangement is provided for ingress processing optimization via traffic classification and grouping. A plurality of packets are classified according to a classification criterion. The classified packets are used to generate a packet bundle containing packets that are uniform with respect to the classification criterion. The packet bundle and its corresponding packet bundle descriptor are transferred to a host which then processes the packet bundle as a whole according to the information contained in the packet bundle descriptor.

Abstract: A digital signal processor may include a plurality of processing elements that are coupled together to accomplish a specialized function. Each processing element may utilize the same shared storage in a form of a plurality of general purpose registers. Each of these registers may be accessed by any of the processing elements. Each register may include a data storage section and a plurality of storage areas for data valid bits that indicate whether the data is valid or not for each of the plurality of processing elements.

Abstract: A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Abstract: A system configuration manager provides a graphical user interface that allows a system administrator to easily administer configuration settings for different computer systems and platforms on a computer network. The system configuration manager of the present invention allows identifying one system configuration or a settings profile as a “model system”. Once the model system is defined, other computer systems may be compared to the model system. Differences between the selected computer systems and the model system are then displayed, and the system configuration manager may be used to update the selected computer systems with configuration settings specified in the model system. Cross-platform support is provided by a configuration mapping mechanism that maps configuration information from one platform to corresponding configuration information for another platform.