Abstract: The present invention provides a TFT array substrate, including a display zone having a plurality of data lines, a plurality of scan lines, and sub-pixels arranged in an array. For the sub-pixels of the same row, a sub-pixel of an even column and a sub-pixel of an odd column that are respectively located at left and right sides of each of the data lines are collectively and electrically connected to the data line each by a TFT. For the sub-pixels of the same row, each of the sub-pixels of the even columns is electrically connected with the scan line above the row of the sub-pixels and each of the sub-pixels of the odd columns is electrically connected with the scan line below the row of the sub-pixels. The non-display zone includes a plurality of fan-out lines. Each of the fan-out lines corresponds to and is connected with one of the scan lines. Each of the fan-out lines includes a horizontal line segment and a slanted line segment.

Abstract: Embodiments of the present disclosure relate to an OLED pixel structure and a method for manufacturing the same, an OLED display panel having the OLED pixel structure, and an OLED display device having the OLED display panel. An OLED pixel structure comprises a plurality of sub-pixel units. Each of said sub-pixel units comprises: a first electrode, an organic material functional layer and a second electrode arranged in that order on said substrate plate; and an intermediate layer arranged between said substrate plate and said first electrode; wherein, a surface of said intermediate layer away from said substrate plate has a recess of arc shape; and said first electrode is located within said recess such that said first electrode, said organic material functional layer and said second electrode each has an arc shape corresponding to the arc shape of said recess.

Abstract: An embodiment of a semiconductor wafer includes a semiconductor substrate, a plurality of through substrate vias (TSVs), and a conductive layer. The TSVs extend between first and second substrate surfaces. The TSVs include a first subset of trench via(s) each having a primary axis aligned in a first direction, and a second subset of trench via(s) each having a primary axis aligned in a second and different direction. The TSVs form an alignment pattern in an alignment area of the substrate. The conductive layer is directly connected to the second substrate surface and to first ends of the TSVs. Using the TSVs for alignment, the conductive layer may be patterned so that a portion of the conductive layer is directly coupled to the TSVs, and so that the conductive layer includes at least one conductive material void (e.g., in alignment with a passive component at the first substrate surface).

Abstract: Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.

Abstract: A light emitting diode (LED) package includes a main vertical LED (VLED) die; a short circuit VLED die; a lens support dam; a transparent lens attached to the lens support dam; a first electrode in electrical communication with a first semiconductor layer of the main VLED die and a second electrode in electrical communication with a second semiconductor layer of the main VLED die.

Abstract: The invention provides a semiconductor device. The semiconductor device includes a buried oxide layer disposed on a substrate. A semiconductor layer having a first conduction type is disposed on the buried oxide layer. A first well doped region having a second conduction type is disposed in the semiconductor layer. A cathode doped region having the second conduction type is disposed in the first well doped region. A first anode doped region having the first conduction type is disposed in the first well doped region, separated from the cathode doped region. A first distance from a bottom boundary of the first anode doped region to a top surface of the semiconductor layer is greater than a second distance from the bottom boundary to an interface between the semiconductor layer and the buried oxide layer.

Abstract: A double self-aligned phase change memory device structure, comprising spaced-apart facing phase change memory film members symmetrically arranged with respect to one another, each of the phase change memory film members at an upper portion thereof being in contact with a separate conductive element, and each of the phase change memory film members being in a range of from 5 nm to 25 nm in thickness. Also described are various methods of making such phase change memory device structure.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern.

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.

Abstract: An array substrate and manufacturing method thereof and a display device. The display device includes a pixel electrode (8), including a first portion (b) in a non-display region and a second portion (a) in a display region; a first electrode (6) formed on the first portion (b) of the pixel electrode (8); a passivation layer (9) formed on the pixel electrode (8) and the first electrode (6), the passivation layer (9) includes a via hole (11) located over the first electrode (6); an active layer (4) and a second electrode (7) that are formed on the passivation layer (9), the active layer (4) being connected to the first electrode (6) through the via hole (11) of the passivation layer (9). With the array substrate and the manufacturing method thereof, the manufacturing cost is reduced, materials of the electrodes are less subjected to corrosion, and quality of the array substrate is enhanced.

Abstract: A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Abstract: A method of fabricating a nano resonator, includes forming a line pattern in a first substrate, and transferring the line pattern to a second substrate including a gate electrode. The method further includes forming a source electrode and a drain electrode on the transferred line pattern.

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer on a top surface of the substrate, and a first semiconductor transistor on the insulating layer, the transistor including an active region with a source region, a drain region, a channel region between the source and drain regions and a gate structure over the channel region, the gate structure extending beyond the transistor to an adjacent area. An outer well is included in the substrate, an inner well of an opposite type as the outer well situated within the outer well and under the active region and adjacent area, and a contact for the inner well in the adjacent area, the contact surrounding the gate structure. Operating the device includes applying a variable voltage at the contact for the inner well, a threshold voltage for the first transistor being altered by the variable voltage. The inner well and gate may be exposed and contacts created therefor together.

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract: A semiconductor device (100) includes: a first line (8) having a first end portion (8T); a second line (2) being insulated from the first line and having a second end portion (2T); a first electrically-conductive portion (9) provided in the neighborhood of the first and second end portions so as to be spaced apart therefrom; a dielectric layer (20) covering them; and a second electrically-conductive portion (38) on the dielectric layer.

Abstract: The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a shaped cavity that this later to be filled with SiGe material. The shape cavity comprises convex regions interfacing the substrate. There are other embodiments as well.

Abstract: Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.

Abstract: A semiconductor device having a stressor is provided. A first trench and a second trench spaced apart from each other are formed in a substrate. A channel area is defined between the first trench and the second trench. A gate dielectric layer is formed on the channel area. A gate electrode is formed on the gate dielectric layer. The stressor includes a plurality of semiconductor layers formed in the first trench and the second trench and a plurality of interlayers formed between the semiconductor layers. Sidewalls of the first trench and the second trench are v-shaped (e.g., have a < or > shape).